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/ThreadX-v6.4.1/utility/rtos_compatibility_layers/posix/
Dpx_cond_broadcast.c95 UINT old_threshold,dummy; in pthread_cond_broadcast() local
131 tx_thread_preemption_change(thread,old_threshold,&dummy); in pthread_cond_broadcast()
144 tx_thread_preemption_change(thread,old_threshold,&dummy); in pthread_cond_broadcast()
Dpx_cond_wait.c97 UINT old_threshold,dummy; in pthread_cond_wait() local
113 tx_thread_preemption_change(thread, old_threshold, &dummy); in pthread_cond_wait()
Dpx_cond_timedwait.c103 UINT old_threshold,dummy; in pthread_cond_timedwait() local
120 tx_thread_preemption_change(thread, old_threshold, &dummy); in pthread_cond_timedwait()
/ThreadX-v6.4.1/ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/SSE-300-MPS3/
Dfvp_sse300_mps3_s.sct41 * This dummy region ensures that the next one will be aligned on a 32 bytes
/ThreadX-v6.4.1/ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/
Dfvp_sse300_mps3_s.sct41 * This dummy region ensures that the next one will be aligned on a 32 bytes