1 /****************************************************************************** 2 TMS320C66xx KeyStone Multicore DSP Software Development Kit (SDK). Rev 2A. 3 (C) MicroLAB Systems, 2014-2015 4 5 File: C66xx DSP SDK API functions declarations 6 ----- 7 8 Notes: 9 ------ 10 1. This C-header file contains C66xx DSP SDK API functions declarations 11 and is used with C66XX.h C-header file. 12 13 2. This file is best viewed with the TAB setting set to '4'. 14 15 ******************************************************************************/ 16 17 18 /** 19 * @file C66XX_FUNCTIONS.hxx 20 * 21 * @brief SDK API functions declarations 22 * 23 * This file contains C66xx DSP SDK API functions declarations 24 * 25 */ 26 27 28 #ifndef __C66XX_FUNCTIONS_HXX__ // check for this file has been already included 29 #define __C66XX_FUNCTIONS_HXX__ 1 30 31 32 33 //============================================================================= 34 //============ Returned error codes =========================================== 35 //============================================================================= 36 /** @addtogroup C66XX_ERRORS DSP SDK API returned error codes 37 * @{ 38 */ 39 #define C66XX_OK 0 /**< No errors */ 40 #define C66XX_PARAM_ERR -1 /**< Invalid function parameter */ 41 #define C66XX_INVALID_HW_ERR -2 /**< Invalid H/W error (invalid board, etc.) */ 42 #define C66XX_HW_ERR -3 /**< H/W error (error writing to the DSP control registers, etc) */ 43 #define C66XX_I2C_ERR -10 /**< I2C module is not correctly operated */ 44 #define C66XX_I2C_AL_ERR -11 /**< I2C module arbitration lost error */ 45 #define C66XX_I2C_RSFULL_ERR -12 /**< I2C module overrun error */ 46 #define C66XX_I2C_XSMT_ERR -13 /**< I2C module underflow error */ 47 #define C66XX_I2C_NACK_ERR -14 /**< I2C module no-acknowledgement error */ 48 #define C66XX_I2C_ARDY_ERR -15 /**< I2C module register-access-ready error */ 49 #define C66XX_I2C_READ_ERR -16 /**< I2C module read error */ 50 #define C66XX_I2C_WRITE_ERR -17 /**< I2C module write error */ 51 #define C66XX_I2C_TIMEOUT_ERR -18 /**< I2C bus timeout error */ 52 /** @}*/ 53 //============================================================================= 54 55 56 57 //============================================================================= 58 //============ SDK API functions ID defs ====================================== 59 //============================================================================= 60 /** @addtogroup C66XX_FUNCTIONS_ID SDK API functions ID defs 61 * @{ 62 */ 63 64 enum 65 { 66 C66XX_GET_ERROR_MESSAGE_FUNCTION_ID = 0, 67 C66XX_GET_FUNCTION_NAME_FUNCTION_ID, 68 C66XX_SYS_SET_CORE_RESET_STATE_FUNCTION_ID, 69 C66XX_SYS_GET_CORE_RESET_STATE_FUNCTION_ID, 70 C66XX_SYS_GET_CORE_RESET_SOURCE_FUNCTION_ID, 71 C66XX_SYS_SET_CORE_BOOT_ADDRESS_FUNCTION_ID, 72 C66XX_SYS_INIT_MAIN_PLL_FUNCTION_ID, 73 C66XX_SYS_GET_MAIN_PLL_SETTINGS_FUNCTION_ID, 74 C66XX_SYS_INIT_DDR3_PLL_FUNCTION_ID, 75 C66XX_SYS_GET_DDR3_PLL_SETTINGS_FUNCTION_ID, 76 C66XX_SYS_INIT_PASS_PLL_FUNCTION_ID, 77 C66XX_SYS_GET_PASS_PLL_SETTINGS_FUNCTION_ID, 78 C66XX_SYS_ENABLE_POWER_DOMAIN_FUNCTION_ID, 79 C66XX_MEM_INIT_XMC_MPAX_SEGMENT_FUNCTION_ID, 80 C66XX_MEM_INIT_DDR3_FUNCTION_ID, 81 C66XX_INT_INIT_CORE_FUNCTION_ID, 82 C66XX_INT_MAP_CORE_EVENT_HANDLER_FUNCTION_ID, 83 C66XX_INT_UNMAP_CORE_EVENT_HANDLER_FUNCTION_ID, 84 C66XX_INT_INIT_CHIP_FUNCTION_ID, 85 C66XX_GPIO_INIT_FUNCTION_ID, 86 C66XX_TIMER_INIT_FUNCTION_ID, 87 C66XX_TIMER_START_FUNCTION_ID, 88 C66XX_TIMER_STOP_FUNCTION_ID, 89 C66XX_TIMER_RESET_FUNCTION_ID, 90 C66XX_TIMER_ENABLE_INTERRUPTS_FUNCTION_ID, 91 C66XX_TIMER_DISABLE_INTERRUPTS_FUNCTION_ID, 92 C66XX_UART_INIT_FUNCTION_ID, 93 C66XX_I2C_INIT_FUNCTION_ID, 94 C66XX_I2C_WRITE_DATA_FUNCTION_ID, 95 C66XX_I2C_READ_DATA_FUNCTION_ID, 96 C66XX_GBE_INIT_SERDES_FUNCTION_ID, 97 C66XX_GBE_INIT_SGMII_FUNCTION_ID, 98 C66XX_SRIO_INIT_FUNCTION_ID, 99 C66XX_SRIO_MAP_TX_QUEUE_FUNCTION_ID, 100 C66XX_SRIO_ROUTE_DOORBELL_INTERRUPT_FUNCTION_ID, 101 C66XX_NUMBER_OF_FUNCTIONS 102 }; 103 /** @}*/ 104 //============================================================================= 105 106 107 108 #ifdef __cplusplus 109 extern "C" { 110 #endif 111 112 113 //============================================================================= 114 //============ General SDK API functions declarations ========================= 115 //============================================================================= 116 117 /** @addtogroup C66XX_GENERAL_FUNCTIONS General DSP SDK API functions 118 * @{ 119 */ 120 121 /*------------ C66XX_get_last_error() function ---------------------------*//** 122 * @brief Function returns error code of last executed API function 123 * 124 * @return Error code of last executed API function 125 * 126 -----------------------------------------------------------------------------*/ 127 int32_t C66XX_get_last_error(void); 128 129 130 /*------------ C66XX_get_error_flag() function ---------------------------*//** 131 * @brief Function returns status of ERROR_FLAG for API functions 132 * 133 * ERROR_FLAG is set by each API function in case error has been detected. 134 * ERROR_FLAG can be reset by C66XX_clear_error_flag() API function 135 * 136 * @param[out] error_code - pointer to a variable to receive the error code in 137 * case error has been detected. In case pointer is NULL, then 138 * no error code is returned; 139 * @param[out] error_function_id - pointer to a variable to receive ID of the 140 * first API function, which has returned with error. In case 141 * pointer is NULL, then no function ID is returned; 142 * 143 * @return Status of ERROR_FLAG: ON or OFF 144 * 145 -----------------------------------------------------------------------------*/ 146 int32_t C66XX_get_error_flag(int32_t *error_code, int32_t *error_function_id); 147 148 149 /*------------ C66XX_clear_error_flag() function -------------------------*//** 150 * @brief Function clear ERROR_FLAG for API functions 151 * 152 * @return Always OK 153 * 154 -----------------------------------------------------------------------------*/ 155 int32_t C66XX_clear_error_flag(void); 156 157 158 /*------------ C66XX_get_error_message() function ------------------------*//** 159 * @brief Function returns the text interpretation of the error code. 160 * 161 * @param[in] error - error code to be interpreted; 162 * @param[out] error_message - pointer to the returned string. In case pointer 163 * is NULL, then no text is filled in; 164 * 165 * @return Error code 166 * 167 -----------------------------------------------------------------------------*/ 168 int32_t C66XX_get_error_message(int32_t error, char *error_message); 169 170 171 /*------------ C66XX_get_function_name() function ------------------------*//** 172 * @brief Function returns the text interpretation of API function. 173 * 174 * @param[in] function_id - ID of the API function to be interpreted; 175 * @param[out] function_name - pointer to the returned string. In case pointer 176 * is NULL, then no text is filled in; 177 * 178 * @return Error code 179 * 180 -----------------------------------------------------------------------------*/ 181 int32_t C66XX_get_function_name(int32_t function_id, char *function_name); 182 183 184 /** @}*/ 185 //============================================================================= 186 187 188 189 //============================================================================= 190 //============ System functions =============================================== 191 //============================================================================= 192 193 /** @addtogroup C66XX_SYS System functions 194 * @{ 195 */ 196 197 198 /** DSP core reset source is global reset */ 199 #define C66XX_DSP_CORE_RESET_SRC_IS_GLOBAL_RESET 1 200 /** DSP core reset source is local reset */ 201 #define C66XX_DSP_CORE_RESET_SRC_IS_LOCAL_RESET 2 202 203 204 /** Main PLL Multiplier bitmask */ 205 #define C66XX_MAIN_PLL_PLLM_BITMASK 0x1fff 206 /** Main PLL Divider bitmask */ 207 #define C66XX_MAIN_PLL_PLLD_BITMASK 0x3f 208 /** Number of PLL dividers */ 209 #define C66XX_MAIN_PLL_PLLDIV_COUNT 16 210 211 /** Main PLL divider data descriptor */ 212 typedef struct 213 { 214 uint32_t enable; /**< PLL divider enable flag */ 215 uint32_t ratio; /**< PLL divider value (8-bit) */ 216 } C66XX_MAIN_PLL_PLLDIV_DD; 217 218 // Main PLL divider data descriptor length in bytes 219 #define C66XX_MAIN_PLL_PLLDIV_DD_LEN sizeof(C66XX_MAIN_PLL_PLLDIV_DD) 220 221 222 /** Main PLL data descriptor (contains parameters which are used to init PLL) */ 223 typedef struct 224 { 225 uint32_t bypass; /**< PLL mode: bypass or not */ 226 uint32_t pllm; /**< PLL multiplier value (13-bit) */ 227 uint32_t plld; /**< PLL divider value (6-bit) */ 228 uint32_t output_divide; /**< PLL output divider value (4-bit) */ 229 C66XX_MAIN_PLL_PLLDIV_DD plldiv[C66XX_MAIN_PLL_PLLDIV_COUNT]; /**< PLL dividers */ 230 } C66XX_MAIN_PLL_DD; 231 232 // Main PLL data descriptor length in bytes 233 #define C66XX_MAIN_PLL_DD_LEN sizeof(C66XX_MAIN_PLL_DD) 234 235 236 /** DDR3 PLL data descriptor (contains parameters which are used to init DDR3 PLL) */ 237 typedef struct 238 { 239 uint32_t pllm; /**< PLL multiplier value (13-bit) */ 240 uint32_t plld; /**< PLL divider value (6-bit) */ 241 } C66XX_DDR3_PLL_DD; 242 243 // DDR3 PLL data descriptor length in bytes 244 #define C66XX_DDR3_PLL_DD_LEN sizeof(C66XX_DDR3_PLL_DD) 245 246 247 /** PASS PLL data descriptor (contains parameters which are used to init PASS PLL) */ 248 typedef struct 249 { 250 uint32_t pllm; /**< PLL multiplier value (13-bit) */ 251 uint32_t plld; /**< PLL divider value (6-bit) */ 252 } C66XX_PASS_PLL_DD; 253 254 // PASS PLL data descriptor length in bytes 255 #define C66XX_PASS_PLL_DD_LEN sizeof(C66XX_PASS_PLL_DD) 256 257 258 /*------------ C66XX_SYS_get_core_number() function ----------------------*//** 259 * @brief Function returns DSP core number at which the program is running 260 * 261 * @return DSP core number 262 * 263 -----------------------------------------------------------------------------*/ 264 uint32_t C66XX_SYS_get_core_number(void); 265 266 267 /*------------ C66XX_SYS_get_max_core_freq() function --------------------*//** 268 * @brief Function returns DSP core max speed in MHz 269 * 270 * @return DSP core max speed in MHz 271 * 272 -----------------------------------------------------------------------------*/ 273 uint32_t C66XX_SYS_get_max_core_freq(void); 274 275 276 /*------------ C66XX_SYS_set_core_reset_state() function -----------------*//** 277 * @brief Function sets or releases DSP core local reset 278 * 279 * @param[in] core - DSP core number to set or release from local reset 280 * @param[in] state - DSP core local reset state: ON or OFF 281 * 282 * @return Error code 283 * 284 -----------------------------------------------------------------------------*/ 285 int32_t C66XX_SYS_set_core_reset_state(uint32_t core, uint32_t state); 286 287 288 /*------------ C66XX_SYS_get_core_reset_state() function -----------------*//** 289 * @brief Function returns DSP core local reset state 290 * 291 * @param[in] core - DSP core number to return local reset state 292 * @param[out] state - pointer to a variable to receive DSP core local reset 293 * state: ON or OFF 294 * 295 * @return Error code 296 * 297 -----------------------------------------------------------------------------*/ 298 int32_t C66XX_SYS_get_core_reset_state(uint32_t core, uint32_t *state); 299 300 301 /*------------ C66XX_SYS_get_core_reset_source() function ----------------*//** 302 * @brief Function returns DSP core reset source: global or local 303 * 304 * @param[in] core - DSP core number to return reset source 305 * @param[out] state - pointer to a variable to receive DSP core reset source: 306 * global or local 307 * 308 * @return Error code 309 * 310 -----------------------------------------------------------------------------*/ 311 int32_t C66XX_SYS_get_core_reset_source(uint32_t core, uint32_t *source); 312 313 314 /*------------ C66XX_SYS_set_core_boot_address() function ----------------*//** 315 * @brief Function sets DSP core boot address. After releasing DSP core from 316 * reset it will start execution from this memory address. 317 * Note that DSP core boot address should be 1024 bytes aligned 318 * 319 * @param[in] core - DSP core number to set boot address 320 * @param[in] addr - DSP core boot address: should be 1024 bytes aligned 321 * 322 * @return Error code 323 * 324 -----------------------------------------------------------------------------*/ 325 int32_t C66XX_SYS_set_core_boot_address(uint32_t core, uint32_t addr); 326 327 328 /*------------ C66XX_SYS_init_main_pll() function ------------------------*//** 329 * @brief Function inits DSP Main PLL according to supplied parameters 330 * 331 * @param[in] pll_dd - Main PLL data descriptor 332 * 333 * @return Error code 334 * 335 -----------------------------------------------------------------------------*/ 336 int32_t C66XX_SYS_init_main_pll(C66XX_MAIN_PLL_DD *pll_dd); 337 338 339 /*------------ C66XX_SYS_get_main_pll_settings() function ----------------*//** 340 * @brief Function returns DSP Main PLL settings 341 * 342 * @param[out] pll_dd - Pointer to a main PLL data descriptor to receive data 343 * 344 * @return Error code 345 * 346 -----------------------------------------------------------------------------*/ 347 int32_t C66XX_SYS_get_main_pll_settings(C66XX_MAIN_PLL_DD *pll_dd); 348 349 350 /*------------ C66XX_SYS_init_ddr3_pll() function ------------------------*//** 351 * @brief Function inits DSP DDR3 PLL according to supplied parameters 352 * 353 * @param[in] ddr3_pll_dd - DDR3 PLL data descriptor 354 * 355 * @return Error code 356 * 357 -----------------------------------------------------------------------------*/ 358 int32_t C66XX_SYS_init_ddr3_pll(C66XX_DDR3_PLL_DD *ddr3_pll_dd); 359 360 361 /*------------ C66XX_SYS_get_ddr3_pll_settings() function ----------------*//** 362 * @brief Function returns DSP DDR3 PLL settings 363 * 364 * @param[out] ddr3_pll_dd - Pointer to DDR3 PLL data descriptor to receive 365 * data 366 * 367 * @return Error code 368 * 369 -----------------------------------------------------------------------------*/ 370 int32_t C66XX_SYS_get_ddr3_pll_settings(C66XX_DDR3_PLL_DD *ddr3_pll_dd); 371 372 373 /*------------ C66XX_SYS_init_pass_pll() function ------------------------*//** 374 * @brief Function inits DSP PASS PLL according to supplied parameters 375 * 376 * @param[in] pass_pll_dd - PASS PLL data descriptor 377 * 378 * @return Error code 379 * 380 -----------------------------------------------------------------------------*/ 381 int32_t C66XX_SYS_init_pass_pll(C66XX_PASS_PLL_DD *pass_pll_dd); 382 383 384 /*------------ C66XX_SYS_get_pass_pll_settings() function ----------------*//** 385 * @brief Function returns DSP PASS PLL settings 386 * 387 * @param[out] pass_pll_dd - Pointer to PASS PLL data descriptor to receive 388 * data 389 * 390 * @return Error code 391 * 392 -----------------------------------------------------------------------------*/ 393 int32_t C66XX_SYS_get_pass_pll_settings(C66XX_PASS_PLL_DD *pass_pll_dd); 394 395 396 /*------------ C66XX_SYS_enable_power_domain() function ------------------*//** 397 * @brief Function powers up selected power domain 398 * 399 * @param[in] domain - power domain number to enable 400 * 401 * @return Error code 402 * 403 -----------------------------------------------------------------------------*/ 404 int32_t C66XX_SYS_enable_power_domain(uint32_t domain); 405 406 407 /** @}*/ 408 //============================================================================= 409 410 411 //============================================================================= 412 //============ DSP memory controller functions ================================ 413 //============================================================================= 414 415 /** @addtogroup C66XX_MEM DSP memory controller functions 416 * @{ 417 */ 418 419 420 /** DSP L1 (P or D) cache sizes */ 421 #define C66XX_CACHE_L1_0KB CACHE_L1_0KCACHE 422 #define C66XX_CACHE_L1_4KB CACHE_L1_4KCACHE 423 #define C66XX_CACHE_L1_8KB CACHE_L1_8KCACHE 424 #define C66XX_CACHE_L1_16KB CACHE_L1_16KCACHE 425 #define C66XX_CACHE_L1_32KB CACHE_L1_32KCACHE 426 #define C66XX_CACHE_L1_MAX_SIZE CACHE_L1_MAXIM3 427 428 429 /** DSP L2 cache sizes */ 430 #define C66XX_CACHE_L2_0KB CACHE_0KCACHE 431 #define C66XX_CACHE_L2_32KB CACHE_32KCACHE 432 #define C66XX_CACHE_L2_64KB CACHE_64KCACHE 433 #define C66XX_CACHE_L2_128KB CACHE_128KCACHE 434 #define C66XX_CACHE_L2_256KB CACHE_256KCACHE 435 #define C66XX_CACHE_L2_512KB CACHE_512KCACHE 436 #define C66XX_CACHE_L2_MAX_SIZE C66XX_CACHE_L2_512KB 437 438 439 /** DDR3 controller initialization data descriptor (contains parameters which are used to init DDR3 controller) */ 440 typedef struct 441 { 442 EMIF4F_TIMING1_CONFIG timing1_config; /**< DDR3 controller Timing 1 configuration */ 443 EMIF4F_TIMING2_CONFIG timing2_config; /**< DDR3 controller Timing 2 configuration */ 444 EMIF4F_TIMING3_CONFIG timing3_config; /**< DDR3 controller Timing 3 configuration */ 445 EMIF4F_SDRAM_CONFIG sdram_config; /**< DDR3 controller SDRAM configuration */ 446 } C66XX_DDR3_EMIF_DD; 447 448 // DDR3 controller initialization data descriptor length in bytes 449 #define C66XX_DDR3_EMIF_DD_LEN sizeof(C66XX_DDR3_EMIF_DD) 450 451 452 /** DDR3 controller physical interface (PHY) data descriptor (contains parameters which are used to perform leveling) */ 453 // All these values should be obtained from DDR3 PHY Calc spreadsheet (sprabl2) provided by TI 454 typedef struct 455 { 456 uint32_t data0_wrlvl_init_ratio; /**< DDR3 byte lane 7 write leveling initialization ratio */ 457 uint32_t data1_wrlvl_init_ratio; /**< DDR3 byte lane 6 write leveling initialization ratio */ 458 uint32_t data2_wrlvl_init_ratio; /**< DDR3 byte lane 5 write leveling initialization ratio */ 459 uint32_t data3_wrlvl_init_ratio; /**< DDR3 byte lane 4 write leveling initialization ratio */ 460 uint32_t data4_wrlvl_init_ratio; /**< DDR3 byte lane 3 write leveling initialization ratio */ 461 uint32_t data5_wrlvl_init_ratio; /**< DDR3 byte lane 2 write leveling initialization ratio */ 462 uint32_t data6_wrlvl_init_ratio; /**< DDR3 byte lane 1 write leveling initialization ratio */ 463 uint32_t data7_wrlvl_init_ratio; /**< DDR3 byte lane 0 write leveling initialization ratio */ 464 uint32_t data8_wrlvl_init_ratio; /**< DDR3 ECC byte lane write leveling initialization ratio */ 465 uint32_t data0_gatelvl_init_ratio; /**< DDR3 byte lane 7 gate leveling initialization ratio */ 466 uint32_t data1_gatelvl_init_ratio; /**< DDR3 byte lane 6 gate leveling initialization ratio */ 467 uint32_t data2_gatelvl_init_ratio; /**< DDR3 byte lane 5 gate leveling initialization ratio */ 468 uint32_t data3_gatelvl_init_ratio; /**< DDR3 byte lane 4 gate leveling initialization ratio */ 469 uint32_t data4_gatelvl_init_ratio; /**< DDR3 byte lane 3 gate leveling initialization ratio */ 470 uint32_t data5_gatelvl_init_ratio; /**< DDR3 byte lane 2 gate leveling initialization ratio */ 471 uint32_t data6_gatelvl_init_ratio; /**< DDR3 byte lane 1 gate leveling initialization ratio */ 472 uint32_t data7_gatelvl_init_ratio; /**< DDR3 byte lane 0 gate leveling initialization ratio */ 473 uint32_t data8_gatelvl_init_ratio; /**< DDR3 ECC byte lane gate leveling initialization ratio */ 474 uint32_t ddr3_config_reg_12_bitmask; /**< DDR3 configuration 12 register bitmask for INVERT_CLK_OUT field */ 475 } C66XX_DDR3_PHY_DD; 476 477 // DDR3 controller initialization data descriptor length in bytes 478 #define C66XX_DDR3_PHY_DD_LEN sizeof(C66XX_DDR3_PHY_DD) 479 480 481 /*------------ C66XX_MEM_set_L1P_cache_size() function -------------------*//** 482 * @brief Function sets DSP L1P cache to the new size 483 * 484 * @param[in] new_size - new size of DSP L1P cache 485 * 486 * @return None 487 * 488 -----------------------------------------------------------------------------*/ 489 void C66XX_MEM_set_L1P_cache_size(uint32_t new_size); 490 491 492 /*------------ C66XX_MEM_get_L1P_cache_size() function -------------------*//** 493 * @brief Function returns DSP L1P cache size 494 * 495 * @return DSP L1P cache size 496 * 497 -----------------------------------------------------------------------------*/ 498 #define C66XX_MEM_get_L1P_cache_size() CACHE_getL1PSize() 499 500 501 /*------------ C66XX_MEM_set_L1D_cache_size() function -------------------*//** 502 * @brief Function sets DSP L1D cache to the new size 503 * 504 * @param[in] new_size - new size of DSP L1D cache 505 * 506 * @return None 507 * 508 -----------------------------------------------------------------------------*/ 509 void C66XX_MEM_set_L1D_cache_size(uint32_t new_size); 510 511 512 /*------------ C66XX_MEM_get_L1D_cache_size() function -------------------*//** 513 * @brief Function returns DSP L1D cache size 514 * 515 * @return DSP L1D cache size 516 * 517 -----------------------------------------------------------------------------*/ 518 #define C66XX_MEM_get_L1D_cache_size() CACHE_getL1DSize() 519 520 521 /*------------ C66XX_MEM_set_L2_cache_size() function --------------------*//** 522 * @brief Function sets DSP L2 cache to the new size 523 * 524 * @param[in] new_size - new size of DSP L2 cache 525 * 526 * @return None 527 * 528 -----------------------------------------------------------------------------*/ 529 void C66XX_MEM_set_L2_cache_size(uint32_t new_size); 530 531 532 /*------------ C66XX_MEM_get_L2_cache_size() function --------------------*//** 533 * @brief Function returns DSP L2 cache size 534 * 535 * @return DSP L2 cache size 536 * 537 -----------------------------------------------------------------------------*/ 538 #define C66XX_MEM_get_L2_cache_size() CACHE_getL2Size() 539 540 541 /*------------ C66XX_MEM_set_memory_region_cache_config() function -------*//** 542 * @brief Function enables or disables DSP caching for specified memory region 543 * 544 * @param[in] mar - MAR register number from 0 to 255 (note that the first 12 545 * memory regions are read-only) 546 * @param[in] cacheable - cache mode to set: ON - enable caching, 547 * OFF - disable caching 548 * @param[in] prefetchable - DSP XMC controller prefetch mode to set: 549 * ON - enable prefetch support, OFF - disable prefetch support 550 * 551 * @return None 552 * 553 -----------------------------------------------------------------------------*/ 554 #define C66XX_MEM_set_memory_region_cache_config(mar, cacheable, prefetchable) CACHE_setMemRegionInfo(mar, cacheable, prefetchable) 555 556 557 /*------------ C66XX_MEM_get_memory_region_cache_config() function -------*//** 558 * @brief Function returns DSP cache configuration for specified memory region 559 * 560 * @param[in] mar - MAR register number from 0 to 255 (note that the first 12 561 * memory regions are read-only) 562 * @param[in] cacheable - pointer to a variable to receive current cache mode: 563 * ON - caching is enabled, OFF - caching is disabled 564 * @param[in] prefetchable - pointer to a variable to receive current DSP XMC 565 * controller prefetch mode: ON - prefetch support is enabled, 566 * OFF - prefetch support is disabled 567 * 568 * @return None 569 * 570 -----------------------------------------------------------------------------*/ 571 #define C66XX_MEM_get_memory_region_cache_config(mar, cacheable, prefetchable) CACHE_getMemRegionInfo(mar, cacheable, prefetchable) 572 573 574 /*------------ C66XX_MEM_init_xmc_mpax_segment() function ----------------*//** 575 * @brief Function configures XMC MPAX segment according to supplied 576 * parameters 577 * 578 * @param[in] index - MPAX segment index from 0 to 15 (note that the first 2 579 * segments are already configured by default) 580 * @param[in] baddr - upper 20 bit of base 32-bit address to remap 581 * @param[in] size - encoded segment size 582 * @param[in] raddr - upper 24 bit of replacement 36-bit address 583 * @param[in] perm - access types allowed in this segment 584 * 585 * @return Error code 586 * 587 -----------------------------------------------------------------------------*/ 588 int32_t C66XX_MEM_init_xmc_mpax_segment(uint32_t index, uint32_t baddr, uint32_t size, uint32_t raddr, uint32_t perm); 589 590 591 /*------------ C66XX_MEM_convert_local_to_global_address() function ------*//** 592 * @brief Function converts local DSP core address to global address 593 * 594 * @param[in] addr - local DSP core address to be converted 595 * 596 * @return Global address 597 * 598 -----------------------------------------------------------------------------*/ 599 uint32_t C66XX_MEM_convert_local_to_global_address(uint32_t addr); 600 601 602 /*------------ C66XX_MEM_init_ddr3() function --------------------------------*//** 603 * @brief Function inits DDR3 controller according to supplied parameters 604 * 605 * @param[in] ddr3_emif_dd - DDR3 controller initialization data descriptor 606 * @param[in] ddr3_phy_dd - DDR3 PHY controller initialization data descriptor 607 * 608 * @return Error code 609 * 610 -----------------------------------------------------------------------------*/ 611 int32_t C66XX_MEM_init_ddr3(C66XX_DDR3_EMIF_DD *ddr3_emif_dd, C66XX_DDR3_PHY_DD *ddr3_phy_dd); 612 613 /** @}*/ 614 //============================================================================= 615 616 617 618 //============================================================================= 619 //============ Timer TSC functions ============================================ 620 //============================================================================= 621 622 /** @addtogroup C66XX_TSC DSP 64-bit Time Stamp Counter (TSC) functions 623 * @{ 624 */ 625 626 /*------------ C66XX_TSC_get_current_value() function --------------------*//** 627 * @brief Function returns DSP TSC current value 628 * 629 * @return 64-bit Time Stamp Counter value 630 * 631 -----------------------------------------------------------------------------*/ 632 uint64_t C66XX_TSC_get_current_value(void); 633 634 635 /*------------ C66XX_TSC_get_duration_s() function -----------------------*//** 636 * @brief Function returns time duration in seconds from Time Stamp Counter 637 * start value 638 * 639 * @param[in] start - 64-bit Time Stamp Counter value 640 * 641 * @return Time duration in seconds 642 * 643 -----------------------------------------------------------------------------*/ 644 double C66XX_TSC_get_duration_s(uint64_t start); 645 646 647 /*------------ C66XX_TSC_set_delay_us() function -------------------------*//** 648 * @brief Function is used to delay the execution for selected number of 649 * microseconds 650 * 651 * @param[in] us - Number of microseconds to delay 652 * 653 * @return None 654 * 655 -----------------------------------------------------------------------------*/ 656 void C66XX_TSC_set_delay_us(uint32_t us); 657 658 /** @}*/ 659 //============================================================================= 660 661 662 663 //============================================================================= 664 //============ C66xx interrupt controller functions =========================== 665 //============================================================================= 666 667 /** @addtogroup C66XX_INT C66xx interrupt controller functions 668 * @{ 669 */ 670 671 672 /** DSP interrupt vector IDs */ 673 #define C66XX_DSP_VECTID_NMI CSL_INTC_VECTID_NMI 674 #define C66XX_DSP_VECTID_4 CSL_INTC_VECTID_4 675 #define C66XX_DSP_VECTID_5 CSL_INTC_VECTID_5 676 #define C66XX_DSP_VECTID_6 CSL_INTC_VECTID_6 677 #define C66XX_DSP_VECTID_7 CSL_INTC_VECTID_7 678 #define C66XX_DSP_VECTID_8 CSL_INTC_VECTID_8 679 #define C66XX_DSP_VECTID_9 CSL_INTC_VECTID_9 680 #define C66XX_DSP_VECTID_10 CSL_INTC_VECTID_10 681 #define C66XX_DSP_VECTID_11 CSL_INTC_VECTID_11 682 #define C66XX_DSP_VECTID_12 CSL_INTC_VECTID_12 683 #define C66XX_DSP_VECTID_13 CSL_INTC_VECTID_13 684 #define C66XX_DSP_VECTID_14 CSL_INTC_VECTID_14 685 #define C66XX_DSP_VECTID_15 CSL_INTC_VECTID_15 686 #define C66XX_DSP_VECTID_COMBINE CSL_INTC_VECTID_COMBINE 687 #define C66XX_DSP_VECTID_EXCEP CSL_INTC_VECTID_EXCEP 688 689 690 /*------------ C66XX_INT_init_core() function ----------------------------*//** 691 * @brief Function initializes C66x CorePac interrupt controller (INTC) using 692 * CSL library. 693 * 694 * If SYS/BIOS RTOS is used, then it's recommended to use the relevant 695 * SYS/BIOS interrupt API (HWI, EventCombiner and CpIntc), as there will be 696 * conflicts since both CSL and SYS/BIOS will use their own Interrupt Service 697 * Table Pointer (ISTP). 698 * 699 * @return Error code 700 * 701 -----------------------------------------------------------------------------*/ 702 int32_t C66XX_INT_init_core(void); 703 704 705 /*------------ C66XX_INT_map_core_event_handler() function ---------------*//** 706 * @brief Function maps DSP interrupt vector to INTC input event ID, plugs 707 * the specified function as DSP interrupt handler function, and enables DSP 708 * interrupt 709 * 710 * @param[in] dsp_vector_id - DSP interrupt vector 711 * @param[in] input_event_id - INTC input event ID 712 * @param[in] handler - pointer to DSP interrupt handler function 713 * 714 * @return Error code 715 * 716 -----------------------------------------------------------------------------*/ 717 int32_t C66XX_INT_map_core_event_handler(uint32_t dsp_vector_id, uint32_t input_event_id, CSL_IntcEventHandler handler); 718 719 720 /*------------ C66XX_INT_unmap_core_event_handler() function -------------*//** 721 * @brief Function unmaps DSP interrupt vector and disables the corresponding 722 * DSP interrupt. 723 * 724 * @param[in] dsp_vector_id - DSP interrupt vector 725 * 726 * @return Error code 727 * 728 -----------------------------------------------------------------------------*/ 729 int32_t C66XX_INT_unmap_core_event_handler(uint32_t dsp_vector_id); 730 731 732 /*------------ C66XX_INT_set_core_dsp_interrupt_handler() function -------*//** 733 * @brief Function sets the specified function as a direct handler for DSP 734 * interrupt vector ID. 735 * 736 * This handler function will be branched to from DSP interrupt vector table 737 * for specified DSP interrupt vector ID, so either it should be declared in C 738 * with "interrupt" keyword or manually save and restore interrupt context and 739 * return with "B IRP" assembler instruction. 740 * The specified DSP interrupt will be enabled too. 741 * 742 * @param[in] dsp_vector_id - DSP interrupt vector 743 * @param[in] isr_handler - direct handler function for DSP interrupt vector 744 * 745 * @return Error code 746 * 747 -----------------------------------------------------------------------------*/ 748 int32_t C66XX_INT_set_core_dsp_interrupt_handler(uint32_t dsp_vector_id, void *isr_handler); 749 750 751 /** Chip interrupt controllers defs */ 752 #define C66XX_CPINTC_ID_0 0 753 #define C66XX_CPINTC_ID_1 1 754 #define C66XX_CPINTC_ID_2 2 755 #define C66XX_CPINTC_ID_3 3 756 757 758 /*------------ C66XX_INT_init_chip() function ----------------------------*//** 759 * @brief Function initializes the specified chip interrupt controller 760 * (CPINTC or CIC) and returns a handle which should be used in all subsequent 761 * CPINTC function calls. 762 * 763 * @param[in] cpintc_id - chip interrupt controller number to initialize (0-3) 764 * 765 * @return Handle to the CPINTC instance: >0 - OK, 766 * 0 - error is occurred 767 * 768 -----------------------------------------------------------------------------*/ 769 uint32_t C66XX_INT_init_chip(uint32_t cpintc_id); 770 771 772 /*------------ C66XX_INT_map_chip_system_to_host_event() function --------*//** 773 * @brief Function maps chip-level event (system event) to CPINTC output event 774 * (host event) end enables it. 775 * 776 * System events are those events generated by a hardware module in the system. 777 * These events are inputs into CPINTC. 778 * Host events are the output events of CPINTC, which act as event inputs to 779 * C66x CorePac interrupt controllers (INTC). 780 * 781 * @param[in] cpintc_handle - chip interrupt controller handle returned by 782 * C66XX_init_cpintc() function call; 783 * @param[in] system_event_id - chip-level (system) event from a hardware 784 * module in the system. 785 * @param[in] host_event_id - CPINTC output event ID 786 * 787 * @return Error code 788 * 789 -----------------------------------------------------------------------------*/ 790 int32_t C66XX_INT_map_chip_system_to_host_event(uint32_t cpintc_handle, uint32_t system_event_id, uint32_t host_event_id); 791 792 793 /*------------ C66XX_INT_enable_chip_host_event() function ---------------*//** 794 * @brief Function enables CPINTC output event (host event). 795 * 796 * @param[in] cpintc_handle - chip interrupt controller handle returned by 797 * C66XX_init_cpintc() function call; 798 * @param[in] host_event_id - CPINTC output event ID to enable 799 * 800 * @return Error code 801 * 802 -----------------------------------------------------------------------------*/ 803 #define C66XX_INT_enable_chip_host_event(cpintc_handle, host_event_id) CSL_CPINTC_enableHostInterrupt(cpintc_handle, host_event_id) 804 805 806 /*------------ C66XX_INT_disable_chip_host_event() function --------------*//** 807 * @brief Function disables CPINTC output event (host event). 808 * 809 * @param[in] cpintc_handle - chip interrupt controller handle returned by 810 * C66XX_init_cpintc() function call; 811 * @param[in] host_event_id - CPINTC output event ID to disable 812 * 813 * @return Error code 814 * 815 -----------------------------------------------------------------------------*/ 816 #define C66XX_INT_disable_chip_host_event(cpintc_handle, host_event_id) CSL_CPINTC_disableHostInterrupt(cpintc_handle, host_event_id) 817 818 819 /*------------ C66XX_INT_clear_chip_system_event() function --------------*//** 820 * @brief Function clears CPINTC input event (system event). 821 * 822 * @param[in] cpintc_handle - chip interrupt controller handle returned by 823 * C66XX_init_cpintc() function call; 824 * @param[in] sys_event_id - CPINTC input event ID to clear 825 * 826 * @return Error code 827 * 828 -----------------------------------------------------------------------------*/ 829 #define C66XX_INT_clear_chip_system_event(cpintc_handle, sys_event_id) CSL_CPINTC_clearSysInterrupt(cpintc_handle, sys_event_id) 830 831 832 /** @}*/ 833 //============================================================================= 834 835 836 837 //============================================================================= 838 //============ General purpose I/O (GPIO) functions =========================== 839 //============================================================================= 840 841 /** @addtogroup C66XX_GPIO DSP GPIO functions 842 * @{ 843 */ 844 845 /** GPIO pins number defs */ 846 enum C66XX_GPIO_PINS 847 { 848 C66XX_GPIO_PIN_0 = 0, 849 C66XX_GPIO_PIN_1, 850 C66XX_GPIO_PIN_2, 851 C66XX_GPIO_PIN_3, 852 C66XX_GPIO_PIN_4, 853 C66XX_GPIO_PIN_5, 854 C66XX_GPIO_PIN_6, 855 C66XX_GPIO_PIN_7, 856 C66XX_GPIO_PIN_8, 857 C66XX_GPIO_PIN_9, 858 C66XX_GPIO_PIN_10, 859 C66XX_GPIO_PIN_11, 860 C66XX_GPIO_PIN_12, 861 C66XX_GPIO_PIN_13, 862 C66XX_GPIO_PIN_14, 863 C66XX_GPIO_PIN_15 864 }; 865 866 /** GPIO pins bitmask defs */ 867 enum C66XX_GPIO_PIN_BITMASKS 868 { 869 C66XX_GPIO_PIN_0_BITMASK = 0x0001, 870 C66XX_GPIO_PIN_1_BITMASK = 0x0002, 871 C66XX_GPIO_PIN_2_BITMASK = 0x0004, 872 C66XX_GPIO_PIN_3_BITMASK = 0x0008, 873 C66XX_GPIO_PIN_4_BITMASK = 0x0010, 874 C66XX_GPIO_PIN_5_BITMASK = 0x0020, 875 C66XX_GPIO_PIN_6_BITMASK = 0x0040, 876 C66XX_GPIO_PIN_7_BITMASK = 0x0080, 877 C66XX_GPIO_PIN_8_BITMASK = 0x0100, 878 C66XX_GPIO_PIN_9_BITMASK = 0x0200, 879 C66XX_GPIO_PIN_10_BITMASK = 0x0400, 880 C66XX_GPIO_PIN_11_BITMASK = 0x0800, 881 C66XX_GPIO_PIN_12_BITMASK = 0x1000, 882 C66XX_GPIO_PIN_13_BITMASK = 0x2000, 883 C66XX_GPIO_PIN_14_BITMASK = 0x4000, 884 C66XX_GPIO_PIN_15_BITMASK = 0x8000 885 }; 886 887 888 /** GPIO bank number for CSL utilities */ 889 #define C66XX_GPIO_BANK_NUMBER 0 890 /** GPIO data definitions */ 891 #define C66XX_GPIO_DATA_OFF 0 892 #define C66XX_GPIO_DATA_ON 1 893 /** GPIO direction definitions */ 894 #define C66XX_GPIO_DIR_OUT 0 895 #define C66XX_GPIO_DIR_IN 1 896 /** GPIO pin edge defs */ 897 #define C66XX_GPIO_PIN_EDGE_RISING 0 898 #define C66XX_GPIO_PIN_EDGE_FALLING 1 899 #define C66XX_GPIO_PIN_EDGE_ANY 2 900 /** GPIO pins bitmask definitions */ 901 #define C66XX_GPIO_DATA_BITMASK 0x0000ffff 902 903 904 /*------------ C66XX_GPIO_init() function --------------------------------*//** 905 * @brief Function inits the GPIO peripheral: all pins are configured as 906 * inputs, interrupts are disabled 907 * 908 * @return Error code 909 * 910 -----------------------------------------------------------------------------*/ 911 int32_t C66XX_GPIO_init(void); 912 913 914 /*------------ C66XX_GPIO_set_pin_direction() function -------------------*//** 915 * @brief Function configures the specified GPIO pin direction 916 * 917 * @param[in] pin_number - GPIO pin number to configure 918 * @param[in] direction - GPIO direction definition 919 * 920 * @return None 921 * 922 -----------------------------------------------------------------------------*/ 923 void C66XX_GPIO_set_pin_direction(uint32_t pin_number, uint32_t direction); 924 925 926 /*------------ C66XX_GPIO_get_pin_direction() function -------------------*//** 927 * @brief Function returns the specified GPIO pin direction 928 * 929 * @param[in] pin_number - GPIO pin number to get direction 930 * 931 * @return GPIO direction definition 932 * 933 -----------------------------------------------------------------------------*/ 934 uint32_t C66XX_GPIO_get_pin_direction(uint32_t pin_number); 935 936 937 /*------------ C66XX_GPIO_set_pin_data() function ------------------------*//** 938 * @brief Function sets the specified GPIO pin state to data 939 * 940 * @param[in] pin_number - GPIO pin number to configure 941 * @param[in] data - GPIO pin state: ON or OFF 942 * 943 * @return None 944 * 945 -----------------------------------------------------------------------------*/ 946 void C66XX_GPIO_set_pin_data(uint32_t pin_number, uint32_t data); 947 948 949 /*------------ C66XX_GPIO_get_pin_data() function ------------------------*//** 950 * @brief Function returns the specified GPIO pin state 951 * 952 * @param[in] pin_number - GPIO pin number to get pin state 953 * 954 * @return GPIO pin state: ON or OFF 955 * 956 -----------------------------------------------------------------------------*/ 957 uint32_t C66XX_GPIO_get_pin_data(uint32_t pin_number); 958 959 960 /*------------ C66XX_GPIO_set_direction() function -----------------------*//** 961 * @brief Function configures the specified GPIO pins direction 962 * 963 * @param[in] pin_bitmask - GPIO pins (ORed) bitmask to configure 964 * @param[in] direction - GPIO direction definition 965 * 966 * @return None 967 * 968 -----------------------------------------------------------------------------*/ 969 void C66XX_GPIO_set_direction(uint32_t pin_bitmask, uint32_t direction); 970 971 972 /*------------ C66XX_GPIO_get_direction() function -----------------------*//** 973 * @brief Function returns the specified GPIO pins direction 974 * 975 * @param[in] pin_bitmask - GPIO pins (ORed) bitmask to get pins direction 976 * 977 * @return Specified GPIO pins direction 978 * 979 -----------------------------------------------------------------------------*/ 980 uint32_t C66XX_GPIO_get_direction(uint32_t pin_bitmask); 981 982 983 /*------------ C66XX_GPIO_set_data() function ----------------------------*//** 984 * @brief Function sets the specified GPIO pins state to data 985 * 986 * @param[in] pin_bitmask - GPIO pins (ORed) bitmask to configure 987 * @param[in] data - GPIO pins state: ON or OFF 988 * 989 * @return None 990 * 991 -----------------------------------------------------------------------------*/ 992 void C66XX_GPIO_set_data(uint32_t pin_bitmask, uint32_t data); 993 994 995 /*------------ C66XX_GPIO_get_data() function ----------------------------*//** 996 * @brief Function returns the specified GPIO pins state 997 * 998 * @param[in] pin_bitmask - GPIO pins (ORed) bitmask to get pins state 999 * 1000 * @return Specified GPIO pins state 1001 * 1002 -----------------------------------------------------------------------------*/ 1003 uint32_t C66XX_GPIO_get_data(uint32_t pin_bitmask); 1004 1005 1006 /*------------ C66XX_GPIO_enable_interrupts() function -------------------*//** 1007 * @brief Function enables GPIO peripheral interrupts 1008 * 1009 * @return None 1010 * 1011 -----------------------------------------------------------------------------*/ 1012 void C66XX_GPIO_enable_interrupts(void); 1013 1014 1015 /*------------ C66XX_GPIO_disable_interrupts() function ------------------*//** 1016 * @brief Function disables GPIO peripheral interrupts 1017 * 1018 * @return None 1019 * 1020 -----------------------------------------------------------------------------*/ 1021 void C66XX_GPIO_disable_interrupts(void); 1022 1023 1024 /*------------ C66XX_GPIO_enable_edge_interrupt() function ---------------*//** 1025 * @brief Function enables the specified GPIO pin edge interrupt 1026 * 1027 * @param[in] pin - GPIO pin number to configure 1028 * @param[in] edge - GPIO pin edge which triggers GPIO interrupt 1029 * 1030 * @return None 1031 * 1032 -----------------------------------------------------------------------------*/ 1033 void C66XX_GPIO_enable_edge_interrupt(uint32_t pin, uint32_t edge); 1034 1035 1036 /*------------ C66XX_GPIO_disable_edge_interrupt() function --------------*//** 1037 * @brief Function disables the specified GPIO pin edge interrupt 1038 * 1039 * @param[in] pin - GPIO pin number to configure 1040 * @param[in] edge - GPIO pin edge which shouldn't trigger GPIO interrupt 1041 * 1042 * @return None 1043 * 1044 -----------------------------------------------------------------------------*/ 1045 void C66XX_GPIO_disable_edge_interrupt(uint32_t pin, uint32_t edge); 1046 1047 1048 /** @}*/ 1049 //============================================================================= 1050 1051 1052 1053 //============================================================================= 1054 //============ Timer module functions ========================================= 1055 //============================================================================= 1056 1057 /** @addtogroup C66XX_TIMER DSP 64-bit Timer module functions 1058 * @{ 1059 */ 1060 1061 1062 /** DSP 64-bit Timer module number defs */ 1063 typedef enum 1064 { 1065 C66XX_TIMER_0 = 0, 1066 C66XX_TIMER_1, 1067 C66XX_TIMER_2, 1068 C66XX_TIMER_3, 1069 C66XX_TIMER_4, 1070 C66XX_TIMER_5, 1071 C66XX_TIMER_6, 1072 C66XX_TIMER_7, 1073 C66XX_TIMER_8, 1074 C66XX_TIMER_9, 1075 C66XX_TIMER_10, 1076 C66XX_TIMER_11, 1077 C66XX_TIMER_12, 1078 C66XX_TIMER_13, 1079 C66XX_TIMER_14, 1080 C66XX_TIMER_15 1081 } C66XX_TIMER; 1082 1083 1084 /** DSP 64-bit Timer mode defs */ 1085 typedef enum 1086 { 1087 C66XX_TIMER_MODE_64BIT_GPT = 0, 1088 C66XX_TIMER_MODE_32BIT_UNCHAINED, 1089 C66XX_TIMER_MODE_64BIT_WDT, 1090 C66XX_TIMER_MODE_32BIT_CHAINED 1091 } C66XX_TIMER_MODE; 1092 1093 1094 /** DSP 64-bit Timer hardware configuration defs */ 1095 typedef enum 1096 { 1097 C66XX_TIMER_HW_CFG_64BIT = 0, 1098 C66XX_TIMER_HW_CFG_32BIT_LOW, 1099 C66XX_TIMER_HW_CFG_32BIT_HIGH 1100 } C66XX_TIMER_HW_CFG; 1101 1102 1103 /** DSP 64-bit Timer count mode defs */ 1104 typedef enum 1105 { 1106 C66XX_TIMER_COUNT_MODE_DISABLED = 0, 1107 C66XX_TIMER_COUNT_MODE_ONE_SHOT, 1108 C66XX_TIMER_COUNT_MODE_CONTINUOUSLY, 1109 C66XX_TIMER_COUNT_MODE_CONTINUOUSLY_RELOAD 1110 } C66XX_TIMER_COUNT_MODE; 1111 1112 1113 /** DSP timer input enable defs */ 1114 typedef enum 1115 { 1116 C66XX_TIMER_CLK_INPUT_DISABLED = 0, 1117 C66XX_TIMER_CLK_INPUT_ENABLED 1118 } C66XX_TIMER_CLK_INPUT; 1119 1120 1121 /** DSP timer input inverter control defs */ 1122 typedef enum 1123 { 1124 C66XX_TIMER_CLK_INPUT_INVERTER_DISABLED = 0, 1125 C66XX_TIMER_CLK_INPUT_INVERTER_ENABLED 1126 } C66XX_TIMER_CLK_INPUT_INVERTER; 1127 1128 1129 /** DSP timer clock source defs */ 1130 typedef enum 1131 { 1132 C66XX_TIMER_CLK_SRC_INTERNAL = 0, 1133 C66XX_TIMER_CLK_SRC_EXTERNAL 1134 } C66XX_TIMER_CLK_SRC; 1135 1136 1137 /** DSP timer clock/pulse mode for timer output defs */ 1138 typedef enum 1139 { 1140 C66XX_TIMER_CLK_OUTPUT_MODE_PULSE = 0, 1141 C66XX_TIMER_CLK_OUTPUT_MODE_CLK 1142 } C66XX_TIMER_CLK_OUTPUT_MODE; 1143 1144 1145 /** DSP timer pulse width used in pulse mode for timer output defs */ 1146 typedef enum 1147 { 1148 C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH_1CLK = 0, 1149 C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH_2CLK, 1150 C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH_3CLK, 1151 C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH_4CLK 1152 } C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH; 1153 1154 1155 /** DSP timer output inverter control defs */ 1156 typedef enum 1157 { 1158 C66XX_TIMER_CLK_OUTPUT_INVERTER_DISABLED = 0, 1159 C66XX_TIMER_CLK_OUTPUT_INVERTER_ENABLED 1160 } C66XX_TIMER_CLK_OUTPUT_INVERTER; 1161 1162 1163 /** DSP 32-bit Timer configuration data descriptor */ 1164 typedef struct 1165 { 1166 C66XX_TIMER_CLK_SRC clk_src; /**< Clock source for 32-bit timer */ 1167 C66XX_TIMER_CLK_INPUT clk_input_enabled; /**< Timer clock is gated by the timer input for 32-bit timer */ 1168 C66XX_TIMER_CLK_INPUT_INVERTER clk_input_inverter_enabled; /**< An inverted timer input drives the 32-bit timer */ 1169 C66XX_TIMER_CLK_OUTPUT_MODE clk_src_output_mode; /**< Clock output mode for 32-bit timer */ 1170 C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH clk_src_output_pulse_width; /**< Clock output pulse width used in pulse mode for 32-bit timer */ 1171 C66XX_TIMER_CLK_OUTPUT_INVERTER clk_output_inverter_enabled; /**< 32-bit timer output is inverted */ 1172 } C66XX_TIMER_32BIT_CFG_DD; 1173 1174 1175 /** DSP 64-bit Timer module configuration data descriptor */ 1176 typedef struct 1177 { 1178 C66XX_TIMER_MODE timer_mode; /**< Timer mode: 64-bit GPT, 64-bit WDT, dual 32-bit unchained or chained */ 1179 C66XX_TIMER_32BIT_CFG_DD timer_high; /**< Configuration data descriptor for 32-bit HIGH timer */ 1180 C66XX_TIMER_32BIT_CFG_DD timer_low; /**< Configuration data descriptor for 32-bit LOW timer */ 1181 } C66XX_TIMER_CFG_DD; 1182 1183 // DSP 64-bit Timer module configuration data descriptor length in bytes 1184 #define C66XX_TIMER_CFG_DD_LEN sizeof(C66XX_TIMER_CFG_DD) 1185 1186 1187 /*------------ C66XX_TIMER_init() function -------------------------------*//** 1188 * @brief Function configures selected DSP 64-bit timer module 1189 * 1190 * @param[in] timer_number - DSP 64-bit timer module number 1191 * @param[in] frequency - DSP timer output frequency in Hz 1192 * @param[in] cfg_dd - pointer to filled DSP 64-bit timer module configuration 1193 * data descriptor 1194 * 1195 * @return Error code 1196 * 1197 -----------------------------------------------------------------------------*/ 1198 int32_t C66XX_TIMER_init(C66XX_TIMER timer_number, uint32_t frequency, C66XX_TIMER_CFG_DD *cfg_dd); 1199 1200 1201 /*------------ C66XX_TIMER_start() function ------------------------------*//** 1202 * @brief Function starts selected DSP timer 1203 * 1204 * @param[in] timer_number - DSP 64-bit timer module number 1205 * @param[in] timer_to_start - hardware timer to start (64BIT/32BIT_LOW/ 1206 * 32BIT_HIGH) 1207 * @param[in] count_mode - DSP timer counting mode (DISABLED/ONE_SHOT/ 1208 * CONTINUOUSLY/CONTINUOUSLY_RELOAD) 1209 * 1210 * @return Error code 1211 * 1212 -----------------------------------------------------------------------------*/ 1213 int32_t C66XX_TIMER_start(C66XX_TIMER timer_number, C66XX_TIMER_HW_CFG timer_to_start, C66XX_TIMER_COUNT_MODE count_mode); 1214 1215 1216 /*------------ C66XX_TIMER_stop() function -------------------------------*//** 1217 * @brief Function stops selected DSP timer 1218 * 1219 * @param[in] timer_number - DSP 64-bit timer module number 1220 * @param[in] timer_to_stop - hardware timer to stop (64BIT/32BIT_LOW/ 1221 * 32BIT_HIGH) 1222 * 1223 * @return Error code 1224 * 1225 -----------------------------------------------------------------------------*/ 1226 int32_t C66XX_TIMER_stop(C66XX_TIMER timer_number, C66XX_TIMER_HW_CFG timer_to_stop); 1227 1228 1229 /*------------ C66XX_TIMER_reset() function ------------------------------*//** 1230 * @brief Function resets selected DSP timer 1231 * 1232 * @param[in] timer_number - DSP 64-bit timer module number 1233 * @param[in] timer_to_reset - hardware timer to reset (64BIT/32BIT_LOW/ 1234 * 32BIT_HIGH) 1235 * 1236 * @return Error code 1237 * 1238 -----------------------------------------------------------------------------*/ 1239 int32_t C66XX_TIMER_reset(C66XX_TIMER timer_number, C66XX_TIMER_HW_CFG timer_to_reset); 1240 1241 1242 /*------------ C66XX_TIMER_enable_interrupts() function ------------------*//** 1243 * @brief Function enables interrupts from selected DSP timer 1244 * 1245 * @param[in] timer_number - DSP 64-bit timer module number 1246 * @param[in] timer_to_enable - hardware timer to enable interrupts from 1247 * (64BIT/32BIT_LOW/32BIT_HIGH) 1248 * 1249 * @return Error code 1250 * 1251 -----------------------------------------------------------------------------*/ 1252 int32_t C66XX_TIMER_enable_interrupts(C66XX_TIMER timer_number, C66XX_TIMER_HW_CFG timer_to_enable); 1253 1254 1255 /*------------ C66XX_TIMER_disable_interrupts() function ------------------*//** 1256 * @brief Function disables interrupts from selected DSP timer 1257 * 1258 * @param[in] timer_number - DSP 64-bit timer module number 1259 * @param[in] timer_to_disable - hardware timer to disable interrupts from 1260 * (64BIT/32BIT_LOW/32BIT_HIGH) 1261 * 1262 * @return Error code 1263 * 1264 -----------------------------------------------------------------------------*/ 1265 int32_t C66XX_TIMER_disable_interrupts(C66XX_TIMER timer_number, C66XX_TIMER_HW_CFG timer_to_disable); 1266 1267 1268 /** @}*/ 1269 //============================================================================= 1270 1271 1272 1273 //============================================================================= 1274 //============ UART functions ================================================= 1275 //============================================================================= 1276 1277 /** @addtogroup C66XX_UART DSP UART functions 1278 * @{ 1279 */ 1280 1281 // UART baud rate defs (max 128 kBauds) 1282 #define C66XX_UART_BAUD_RATE_2400 2400 /**< UART baud rate 2400 bps */ 1283 #define C66XX_UART_BAUD_RATE_4800 4800 /**< UART baud rate 4800 bps */ 1284 #define C66XX_UART_BAUD_RATE_9600 9600 /**< UART baud rate 9600 bps */ 1285 #define C66XX_UART_BAUD_RATE_19200 19200 /**< UART baud rate 19200 bps */ 1286 #define C66XX_UART_BAUD_RATE_38400 38400 /**< UART baud rate 38400 bps */ 1287 #define C66XX_UART_BAUD_RATE_57600 57600 /**< UART baud rate 57600 bps */ 1288 #define C66XX_UART_BAUD_RATE_115200 115200 /**< UART baud rate 115200 bps */ 1289 1290 // UART data bits defs 1291 #define C66XX_UART_DATA_BITS_5BITS 5 /**< UART 5-bits data words */ 1292 #define C66XX_UART_DATA_BITS_6BITS 6 /**< UART 6-bits data words */ 1293 #define C66XX_UART_DATA_BITS_7BITS 7 /**< UART 7-bits data words */ 1294 #define C66XX_UART_DATA_BITS_8BITS 8 /**< UART 8-bits data words */ 1295 1296 // UART parity parameter defs 1297 #define C66XX_UART_PARITY_NONE 0 /**< no parity */ 1298 #define C66XX_UART_PARITY_EVEN 1 /**< even parity */ 1299 #define C66XX_UART_PARITY_ODD 2 /**< odd parity */ 1300 1301 // UART stop bits defs 1302 #define C66XX_UART_STOP_BITS_1BIT 0 /**< one stop bit */ 1303 #define C66XX_UART_STOP_BITS_1_5BITS 1 /**< one and a half stop bits */ 1304 #define C66XX_UART_STOP_BITS_2BITS 2 /**< two stop bits */ 1305 1306 // UART key defs 1307 #define C66XX_UART_KEY_BEEP 0x7 /**< BELL value in HEX */ 1308 #define C66XX_UART_KEY_ESC 0x1b /**< ESC value in HEX */ 1309 #define C66XX_UART_KEY_CR 0xd /**< Carriage Return value in HEX */ 1310 #define C66XX_UART_KEY_BS 0x8 /**< Back space value in HEX */ 1311 #define C66XX_UART_LINE_LEN_MAX 80 /**< Maximum available received line length */ 1312 1313 1314 1315 /*------------ C66XX_UART_init() function --------------------------------*//** 1316 * @brief Function inits the UART peripheral 1317 * 1318 * @param[in] core_clk - DSP core clock frequency in MHz; 1319 * @param[in] baud_rate - desired baud rate; 1320 * @param[in] data_bits - number of data bits; 1321 * @param[in] parity - parity bit; 1322 * @param[in] stop_bits - number of stop bits; 1323 * 1324 * @return Error code 1325 * 1326 -----------------------------------------------------------------------------*/ 1327 int32_t C66XX_UART_init(uint32_t core_clk, uint32_t baud_rate, uint32_t data_bits, uint32_t parity, uint32_t stop_bits); 1328 1329 1330 /*------------ C66XX_UART_receiver_is_ready() function -------------------*//** 1331 * @brief Function checks if a character is received over UART 1332 * 1333 * @return 1 - a character is received over UART, 1334 * 0 - otherwise 1335 * 1336 -----------------------------------------------------------------------------*/ 1337 uint32_t C66XX_UART_receiver_is_ready(void); 1338 1339 1340 /*------------ C66XX_UART_receive_char() function ------------------------*//** 1341 * @brief Function receives a character over UART 1342 * 1343 * @return Received character 1344 * 1345 -----------------------------------------------------------------------------*/ 1346 uint8_t C66XX_UART_receive_char(void); 1347 1348 1349 /*------------ C66XX_UART_transmit_char() function -----------------------*//** 1350 * @brief Function transmits a character over UART 1351 * 1352 * @param[in] c - A character to transmit 1353 * 1354 * @return None 1355 * 1356 -----------------------------------------------------------------------------*/ 1357 void C66XX_UART_transmit_char(uint8_t c); 1358 1359 1360 /*------------ C66XX_UART_transmit_string() function ---------------------*//** 1361 * @brief Function transmits a string until '0' character 1362 * 1363 * @param[in] s - A pointer to the string to transmit 1364 * 1365 * @return None 1366 * 1367 -----------------------------------------------------------------------------*/ 1368 void C66XX_UART_transmit_string(char *s); 1369 1370 1371 /*------------ C66XX_UART_receive_line_string() function -----------------*//** 1372 * @brief Function receives a line ended with CR character, and stores 1373 * received characters into string with '\0' symbol. 1374 * 1375 * Note that maximum received line length should not exceed 1376 * C66XX_UART_LINE_LEN_MAX value! 1377 * 1378 * @param[in] s - Pointer to a string to store received characters 1379 * 1380 * @return Number of received characters without '\0' symbol. 1381 * 1382 -----------------------------------------------------------------------------*/ 1383 uint32_t C66XX_UART_receive_line_string(char *s); 1384 1385 1386 /** @}*/ 1387 //============================================================================= 1388 1389 1390 1391 //============================================================================= 1392 //============ I2C functions ================================================== 1393 //============================================================================= 1394 1395 /** @addtogroup C66XX_I2C DSP I2C functions 1396 * @{ 1397 */ 1398 1399 1400 // I2C interrupt codes 1401 #define C66XX_I2C_INTCODE_NONE 0 /**< No interrupt */ 1402 #define C66XX_I2C_INTCODE_AL 1 /**< Arbitration-lost interrupt */ 1403 #define C66XX_I2C_INTCODE_NACK 2 /**< No-acknowledge interrupt */ 1404 #define C66XX_I2C_INTCODE_ARDY 3 /**< Register-access-ready interrupt */ 1405 #define C66XX_I2C_INTCODE_ICRRDY 4 /**< Receive-data-ready interrupt */ 1406 #define C66XX_I2C_INTCODE_ICXRDY 5 /**< Transmit-data-ready interrupt */ 1407 #define C66XX_I2C_INTCODE_SCD 6 /**< Stop-condition-detected interrupt */ 1408 #define C66XX_I2C_INTCODE_AAS 7 /**< Address-as-slave interrupt */ 1409 1410 1411 /*------------ C66XX_I2C_init() function ---------------------------------*//** 1412 * @brief Function inits the I2C peripheral 1413 * 1414 * @param[in] core_clk - DSP core clock frequency in MHz; 1415 * @param[in] i2c_clk - I2C clock in Hz; 1416 * @param[in] own_addr - I2C own slave address; 1417 * 1418 * @return Error code 1419 * 1420 -----------------------------------------------------------------------------*/ 1421 int32_t C66XX_I2C_init(uint32_t core_clk, uint32_t i2c_clk, uint32_t own_addr); 1422 1423 1424 /*------------ C66XX_I2C_write_data() function ---------------------------*//** 1425 * @brief Function writes data[len] to I2C chip_addr at mem_addr memory 1426 * address 1427 * 1428 * @param[in] chip_addr - I2C chip address; 1429 * @param[in] mem_addr - memory (register) address within the chip; 1430 * @param[in] mem_addr_len - number of bytes to use for mem_addr (typically 1, 1431 * 2 for larger memories, 0 for register type devices with only 1432 * one register); 1433 * @param[in] data - pointer to data; 1434 * @param[in] len - data len in bytes; 1435 * 1436 * @return Error code 1437 * 1438 -----------------------------------------------------------------------------*/ 1439 int32_t C66XX_I2C_write_data(uint8_t chip_addr, uint32_t mem_addr, uint32_t mem_addr_len, uint8_t *data, uint32_t len); 1440 1441 1442 /*------------ C66XX_I2C_read_data() function ----------------------------*//** 1443 * @brief Function reads data[len] from I2C chip_addr at mem_addr memory 1444 * 1445 * @param[in] chip_addr - I2C chip address; 1446 * @param[in] mem_addr - memory (register) address within the chip; 1447 * @param[in] mem_addr_len - number of bytes to use for mem_addr (typically 1, 1448 * 2 for larger memories, 0 for register type devices with only 1449 * one register); 1450 * @param[out] buf - pointer to data buffer to store data; 1451 * @param[in] len - data len in bytes; 1452 * 1453 * @return Error code 1454 * 1455 -----------------------------------------------------------------------------*/ 1456 int32_t C66XX_I2C_read_data(uint8_t chip_addr, uint32_t mem_addr, uint32_t mem_addr_len, uint8_t *buf, uint32_t len); 1457 1458 1459 /** @}*/ 1460 //============================================================================= 1461 1462 1463 1464 //============================================================================= 1465 //============ Gigabit Ethernet (GbE) Switch functions ======================== 1466 //============================================================================= 1467 1468 /** @addtogroup C66XX_GBE DSP Gigabit Ethernet Switch functions 1469 * @{ 1470 */ 1471 1472 /*------------ C66XX_GBE_get_mac_id() function ---------------------------*//** 1473 * @brief Function returns DSP MAC address for this device 1474 * 1475 * @return 64-bit variable that contains 48-bit MAC ID 1476 * 1477 -----------------------------------------------------------------------------*/ 1478 uint64_t C66XX_GBE_get_mac_id(void); 1479 1480 1481 /*------------ C66XX_GBE_init_serdes() function --------------------------*//** 1482 * @brief Function inits Gigabit Ethernet Serdes block to the default state 1483 * 1484 * @return Error code 1485 * 1486 -----------------------------------------------------------------------------*/ 1487 int32_t C66XX_GBE_init_serdes(void); 1488 1489 1490 /** SGMII port Slave operation mode */ 1491 #define C66XX_SGMII_PORT_SLAVE_MODE 0 1492 /** SGMII port Master operation mode */ 1493 #define C66XX_SGMII_PORT_MASTER_MODE 1 1494 1495 1496 /** SGMII port autonegotiation disabled */ 1497 #define C66XX_SGMII_PORT_AUTONEGOTIATION_DISABLED 0 1498 /** SGMII port autonegotiation enabled */ 1499 #define C66XX_SGMII_PORT_AUTONEGOTIATION_ENABLED 1 1500 1501 1502 /*------------ C66XX_GBE_init_sgmii() function ---------------------------*//** 1503 * @brief Function inits Gigabit Ethernet SGMII block 1504 * 1505 * Note that this function requires the presence of link partner connected 1506 * at specified SGMII port - PHY or another SGMII. 1507 * 1508 * @param[in] port - MAC port number for which the SGMII port setup should 1509 * be performed 1510 * @param[in] mode - SGMII port operation mode: master or slave. 1511 * @param[in] autoneg - flag to enable autonegotiation on this SGMII port. 1512 * 1513 * @return Error code 1514 * 1515 -----------------------------------------------------------------------------*/ 1516 int32_t C66XX_GBE_init_sgmii(uint32_t port, uint32_t mode, uint32_t autoneg); 1517 1518 1519 /** @}*/ 1520 //============================================================================= 1521 1522 1523 1524 //============================================================================= 1525 //============ SRIO functions ================================================= 1526 //============================================================================= 1527 1528 /** @addtogroup C66XX_SRIO DSP SRIO functions 1529 * @{ 1530 */ 1531 1532 /** SRIO vendor identifier */ 1533 #define C66XX_SRIO_DEVICE_VENDOR_ID 0x30 1534 /** SRIO device revision */ 1535 #define C66XX_SRIO_DEVICE_REVISION 0x0 1536 /** SRIO assembly identifier */ 1537 #define C66XX_SRIO_DEVICE_ASSEMBLY_ID 0x0 1538 /** SRIO assembly vendor identifier */ 1539 #define C66XX_SRIO_DEVICE_ASSEMBLY_VENDOR_ID C66XX_SRIO_DEVICE_VENDOR_ID 1540 /** SRIO assembly device revision */ 1541 #define C66XX_SRIO_DEVICE_ASSEMBLY_REVISION C66XX_SRIO_DEVICE_REVISION 1542 /** SRIO assembly extension features */ 1543 #define C66XX_SRIO_DEVICE_ASSEMBLY_FEATURES 0x0100 1544 1545 1546 /** SRIO link rate 1.25 Gbps */ 1547 #define C66XX_SRIO_LINK_RATE_1_25GB 1 1548 /** SRIO link rate 2.5 Gbps */ 1549 #define C66XX_SRIO_LINK_RATE_2_5GB 2 1550 /** SRIO link rate 3.125 Gbps */ 1551 #define C66XX_SRIO_LINK_RATE_3_125GB 3 1552 /** SRIO link rate 5 Gbps */ 1553 #define C66XX_SRIO_LINK_RATE_5GB 4 1554 1555 1556 // SRIO port widths defs - corresponds to SRIO path modes 1557 /** SRIO port width with 1 receive and transmit lane */ 1558 #define C66XX_SRIO_PORT_WIDTH_1X 0 1559 /** SRIO port width with 2 receive and transmit lanes */ 1560 #define C66XX_SRIO_PORT_WIDTH_2X 3 1561 /** SRIO port width with 4 receive and transmit lanes */ 1562 #define C66XX_SRIO_PORT_WIDTH_4X 4 1563 1564 1565 /** SRIO port 0 */ 1566 #define C66XX_SRIO_PORT_0 0 1567 /** SRIO port 1 */ 1568 #define C66XX_SRIO_PORT_1 1 1569 /** SRIO port 2 */ 1570 #define C66XX_SRIO_PORT_2 2 1571 /** SRIO port 3 */ 1572 #define C66XX_SRIO_PORT_3 3 1573 1574 1575 /** SRIO peripheral normal operation mode */ 1576 #define C66XX_SRIO_OPMODE_NORMAL 0 1577 /** SRIO peripheral loopback operation mode - used to test the peripheral */ 1578 #define C66XX_SRIO_OPMODE_LOOPBACK 1 1579 1580 1581 /** SRIO device identificator data descriptor */ 1582 typedef struct 1583 { 1584 uint32_t dev_id_8bit; /**< SRIO 8-bit device identificator */ 1585 uint32_t dev_id_16bit; /**< SRIO 16-bit device identificator */ 1586 } C66XX_SRIO_DEVICE_ID_DD; 1587 1588 // SRIO device identificator data descriptor length in bytes 1589 #define C66XX_SRIO_DEVICE_ID_DD_LEN sizeof(C66XX_SRIO_DEVICE_ID_DD) 1590 1591 1592 /** SRIO destination device identificators number */ 1593 #define C66XX_SRIO_DESTINATION_DEVICE_ID_COUNT 4 1594 1595 1596 /** SRIO messages (Type9 and Type11) transmit queues mapping data descriptor */ 1597 typedef struct 1598 { 1599 uint32_t port; /**< SRIO port to which the queue is mapped */ 1600 uint32_t priority; /**< priority bit */ 1601 } C66XX_SRIO_TX_QUEUE_SCH_DD; 1602 1603 // SRIO messages (Type9 and Type11) transmit queues mapping data descriptor length in bytes 1604 #define C66XX_SRIO_TX_QUEUE_SCH_DD_LEN sizeof(C66XX_SRIO_TX_QUEUE_SCH_DD) 1605 1606 1607 /** SRIO peripheral initialization data descriptor */ 1608 typedef struct 1609 { 1610 uint32_t mode; /**< SRIO peripheral operation mode */ 1611 uint32_t link_rate; /**< SRIO link rate definition */ 1612 uint32_t port_width; /**< SRIO port width definition (1x, 2x, or 4x) */ 1613 C66XX_SRIO_DEVICE_ID_DD src_dev_id_dd; /**< SRIO base device identificators */ 1614 C66XX_SRIO_DEVICE_ID_DD dst_dev_id_dd[C66XX_SRIO_DESTINATION_DEVICE_ID_COUNT]; /**< SRIO destination device identificators */ 1615 } C66XX_SRIO_DD; 1616 1617 // SRIO peripheral initialization data descriptor length in bytes 1618 #define C66XX_SRIO_DD_LEN sizeof(C66XX_SRIO_DD) 1619 1620 1621 /*------------ C66XX_SRIO_init() function --------------------------------*//** 1622 * @brief Function inits the SRIO peripheral 1623 * 1624 * The function does the following: 1625 * 1. SRIO peripheral supports directIO, doorbell, data messaging (Type9 1626 * packets) and data streaming (Type11 packets) operations. 1627 * 2. Max MTU length is set to 256 bytes. 1628 * 3. SRIO 8-bit and 16-bit base device IDs are set to supplied parameters. 1629 * 4. Available destination SRIO 8-bit and 16-bit device IDs are set 1630 * according to supplied parameters. 1631 * 5. Operation mode is set according to supplied parameter. 1632 * 6. Link rate and ports configuration (4 ports are available) are set 1633 * according to supplied parameters. 1634 * 7. SRIO transmit queues used in data message (Type9 and Type11) operations 1635 * are configured by default: all 16 queues send packets onto Port 0 and 1636 * operate at the same minimum priority level. In case the different mapping 1637 * is needed then C66XX_srio_map_tx_queue() function should be called. 1638 * 8. 64 SRIO doorbell interrupts are configured by default: the first 16 1639 * interrupts (0-15) are routed to INTDST16 (Interrupt destination 16), 1640 * 16-31 - to INTDST17 (Interrupt destination 17), 32-47 - to INTDST18 1641 * (Interrupt destination 18), 48-63 - to INTDST19 (Interrupt destination 1642 * 19). In case the different interrupt routing is needed then 1643 * C66XX_srio_route_doorbell_interrupt() function should be called. 1644 * 9. GARBAGE queues, which can used by the TXU, are not configured. 1645 * 1646 * @param[in] srio_dd - SRIO peripheral initialization data descriptor 1647 * 1648 * @return Error code 1649 * 1650 -----------------------------------------------------------------------------*/ 1651 int32_t C66XX_SRIO_init(C66XX_SRIO_DD *srio_dd); 1652 1653 1654 /*------------ C66XX_SRIO_map_tx_queue() function ------------------------*//** 1655 * @brief Function configures the selected SRIO transmit queue according to 1656 * supplied parameters: SRIO port to which the queue is mapped and priority 1657 * bit 1658 * 1659 * @param[in] queue - transmit queue number (0 - 15) 1660 * @param[in] tx_queue_sch_dd - transmit queue mapping data descriptor 1661 * 1662 * @return Error code 1663 * 1664 -----------------------------------------------------------------------------*/ 1665 int32_t C66XX_SRIO_map_tx_queue(uint32_t queue, C66XX_SRIO_TX_QUEUE_SCH_DD *tx_queue_sch_dd); 1666 1667 1668 /*------------ C66XX_SRIO_route_doorbell_interrupt() function ------------*//** 1669 * @brief Function configures the selected SRIO doorbell interrupt to 1670 * specified interrupt destination number 1671 * 1672 * @param[in] doorbell - SRIO doorbell interrupt number (0 - 63) 1673 * @param[in] intdst - interrupt destination number (0 - 23) 1674 * 1675 * @return Error code 1676 * 1677 -----------------------------------------------------------------------------*/ 1678 int32_t C66XX_SRIO_route_doorbell_interrupt(uint32_t doorbell, uint32_t intdst); 1679 1680 1681 /** @}*/ 1682 //============================================================================= 1683 1684 1685 1686 #ifdef __cplusplus 1687 } 1688 #endif 1689 1690 1691 1692 //============================================================================= 1693 #endif /* __C66XX_FUNCTIONS_HXX__ */ 1694
