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/ThreadX-v6.4.1/utility/rtos_compatibility_layers/OSEK/
Dos.h542 TickType cycle; member
549 TickType cycle; member
769 TickType cycle; member
919 StatusType SetAbsAlarm(AlarmType AlarmID, TickType start, TickType cycle);
920 StatusType SetRelAlarm(AlarmType AlarmID, TickType increment, TickType cycle);
Dtx_osek.c4218 if (this_alarm->cycle != 0u) in IncrCounter()
4221 this_alarm->expiration_count += this_alarm->cycle; in IncrCounter()
4727 this_alarm->cycle = 0u; in CreateAlarm()
4754 this_alarm->cycle = Cycle; in CreateAlarm()
4889 StatusType SetAbsAlarm(AlarmType AlarmID, TickType start, TickType cycle) in SetAbsAlarm() argument
4898 service_SetAbsAlarm.cycle = cycle; in SetAbsAlarm()
4937 if (cycle != 0u) in SetAbsAlarm()
4939 if ((cycle < osek_alarm->min_cyc) || ( cycle > osek_alarm->max_allowed_value)) in SetAbsAlarm()
4951 osek_alarm->cycle = cycle; in SetAbsAlarm()
5012 StatusType SetRelAlarm(AlarmType AlarmID, TickType increment, TickType cycle) in SetRelAlarm() argument
[all …]
/ThreadX-v6.4.1/ports/cortex_m3/ghs/example_build/
Dtx_initialize_low_level.arm93 /* Enable the cycle count register. */
98 STR r1, [r0] ; Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m7/ghs/example_build/
Dtx_initialize_low_level.arm93 /* Enable the cycle count register. */
98 STR r1, [r0] ; Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m4/ghs/example_build/
Dtx_initialize_low_level.arm93 /* Enable the cycle count register. */
98 STR r1, [r0] ; Enable the cycle count register
/ThreadX-v6.4.1/ports_arch/ARMv7-M/threadx/ghs/example_build/
Dtx_initialize_low_level.arm93 /* Enable the cycle count register. */
98 STR r1, [r0] ; Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m7/iar/example_build/
Dtx_initialize_low_level.s104 STR r1, [r0] ; Enable the cycle count register
/ThreadX-v6.4.1/ports_module/cortex_m3/iar/example_build/
Dtx_initialize_low_level.s114 STR r1, [r0] ; Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m3/iar/example_build/
Dtx_initialize_low_level.s104 STR r1, [r0] ; Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m4/iar/example_build/
Dtx_initialize_low_level.s104 STR r1, [r0] ; Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m0/gnu/example_build/
Dtx_initialize_low_level.S116 @ STR r1, [r0] @ Enable the cycle count register
/ThreadX-v6.4.1/ports_module/cortex_m3/gnu/example_build/
Dtx_initialize_low_level.S113 STR r1, [r0] @ Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m0/ac6/example_build/sample_threadx/
Dtx_initialize_low_level.S100 @ STR r1, [r0] @ Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m0/iar/example_build/
Dtx_initialize_low_level.s107 ; STR r1, [r0] ; Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m3/ac6/example_build/sample_threadx/
Dtx_initialize_low_level.S120 STR r1, [r0] @ Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m4/ac6/example_build/sample_threadx/
Dtx_initialize_low_level.S120 STR r1, [r0] @ Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m7/ac6/example_build/sample_threadx/
Dtx_initialize_low_level.S120 STR r1, [r0] @ Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m4/gnu/example_build/
Dtx_initialize_low_level.S126 STR r1, [r0] @ Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m3/ac5/example_build/
Dtx_initialize_low_level.s159 ; STR r1, [r0] ; Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m3/keil/example_build/
Dtx_initialize_low_level.s158 ; STR r1, [r0] ; Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m4/ac5/example_build/
Dtx_initialize_low_level.s163 ; STR r1, [r0] ; Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m7/ac5/example_build/
Dtx_initialize_low_level.s168 ; STR r1, [r0] ; Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m4/keil/example_build/
Dtx_initialize_low_level.s178 ; STR r1, [r0] ; Enable the cycle count register
/ThreadX-v6.4.1/ports_module/cortex_m3/ac5/example_build/
Dtx_initialize_low_level.S182 ; STR r1, [r0] ; Enable the cycle count register
/ThreadX-v6.4.1/ports/cortex_m0/ac5/example_build/
Dtx_initialize_low_level.s158 ; STR r1, [r0] ; Enable the cycle count register

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