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/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/example_build/
Dinit_caches2.S71 li a2, 2 // Used to test against
72 beq a2, a3, Isets_done // if IS = 2
76 lui a2, 0x8000 // Get a KSeg0 address for cacheops
81 cache 0x8, 0(a2) // Index Store tag Cache opt
84 add a2, v1 // Increment line address by line size
107 li a2, 2 // Used to test against
108 beq a2, a3, Dsets_done // if DS = 2
112 lui a2, 0x8000 // Get a KSeg0 address for cacheops
117 cache 0x9, 0(a2) // Index Store tag Cache opt
120 add a2, v1 // Increment line address by line size
[all …]
Dinit_L23caches.S132 li a2, 2
133 sllv v1, a2, v1 // Now have true L2$ line size in bytes
137 li a2, 64
138 sllv a0, a2, a0 // L2$ Sets per way
147 lui a2, 0x8000 // Get a KSeg0 address for cacheops
157 cache 0xB, 0(a2) // Write Tag using index store tag
161 add a2, v1 // Get next line address
172 li a2, 2
173 sllv v1, a2, v1 // Decode L3$ line size in bytes
177 li a2, 64
[all …]
Dstart.S189 la a2,init_gpr // Fill register file with set value.
190 jalr a2
192 la a2, set_gpr_boot_values // Fill register file boot info.
193 jalr a2
211 la a2, init_cp0 // Init CP0 Status, Count, Compare, Watch*, and Cause.
212 jalr a2
233 la a2, init_tlb // Generate unique EntryHi contents per entry pair.
234 jalr a2
238 la a2, init_gic // Configure the global interrupt controller.
239 jalr a2
[all …]
/ThreadX-v6.4.1/ports/xtensa/xcc/src/
Dtx_thread_system_return.S88 addi a2, sp, -XT_STK_FRMSZ /* avoid addi/addmi relaxation that */
89 mov sp, a2 /* might temporarily move sp up */
121 rsr.ps a2
124 s32i a2, sp, XT_STK_PS /* save PS */
132 movi a2, PS_STACK_KERNEL | PS_DI /* Set PS.STACK = Kernel and */
134 xps a2, a8
137 movi a2, TX_TRUE
140 s32i a2, a4, tx_thread_solicited /* mark as solicited switch */
153 addi a2, sp, -XT_STK_FRMSZ
154 s32i a2, a4, tx_thread_stack_ptr /* Save SP in TCB */
[all …]
Dtx_thread_schedule.S80 movi a2, PS_STACK_KERNEL | PS_DI /* Set PS.STACK = Kernel and */
82 xps a2, a3
123 XT_INTS_DISABLE(a2) /* disable interrupts if not already */
124 l32i a2, a3, 0 /* a2 = _tx_thread_execute_ptr */
125 bnez a2, .L_tx_thread_schedule_ready
141 l32i a0, a2, tx_thread_run_count
142 s32i a2, a3, 0 /* a2 = _tx_thread_current_ptr (TCB) */
148 s32i a3, a2, tx_thread_run_count
152 l32i a3, a2, tx_thread_time_slice
166 l32i a3, a2, tx_thread_clib_ptr
[all …]
Dtx_thread_context_restore.S99 movi a2, _tx_thread_system_state /* a2 = & interrupt nesting count */
100 l32i a3, a2, 0 /* decrement interrupt nesting count */
102 s32i a3, a2, 0
116 l32i a2, a0, 0 /* a2 = _tx_thread_current_ptr (old) */
118 beqz a2, .L_tx_thread_idle_system_restore
121 beq a3, a2, .L_tx_thread_no_preempt_restore
136 l32i a3, a2, tx_thread_stack_ptr /* a3 = thread's stack ptr */
158 s32i a4, a2, tx_thread_time_slice
173 s16i a3, a2, tx_thread_cp_state + XT_CPENABLE
197 l32i sp, a2, tx_thread_stack_ptr
Dtx_timer_interrupt.S91 movi a2, tx_timer_user_isr
92 beqz a2, 1f
94 callx0 a2
96 callx8 a2
124 movi a2, _tx_timer_system_clock /* a2 = &_tx_timer_system_clock */
125 l32i a3, a2, 0 /* a3 = _tx_timer_system_clock++ */
127 s32i a3, a2, 0
131 movi a2, XT_TICK_DIVISOR /* a2 = comparator increment */
134 l32i a2, a3, 0 /* a2 = comparator increment */
137 add a4, a3, a2 /* a4 = new comparator value */
[all …]
Dxtensa_context.S100 s32i a2, sp, XT_STK_A2
194 addi a2, sp, XT_STK_EXTRA /* where to save it */
197 and a2, a2, a3 /* align dynamically >16 bytes */
249 addi a2, sp, XT_STK_EXTRA /* where to find it */
252 and a2, a2, a3 /* align dynamically >16 bytes */
259 l32i a2, sp, XT_STK_LBEG
261 wsr a2, LBEG
262 l32i a2, sp, XT_STK_LCOUNT
264 wsr a2, LCOUNT
269 l32i a2, sp, XT_STK_ATOMCTL
[all …]
Dxtensa_coproc_handler.S104 mov a5, a2 // a5 = CP index n
118 extui a2, a0, 0, 16 // coprocessor bitmask portion
119 or a4, a4, a2 // a4 = CPENABLE | (1 << n)
124 l32i a2, a3, 0 // a2 = old owner's save area
129 beq a15, a2, .L_xt_coproc_done // new owner == old, we're done
132 beqz a2, .L_check_new
135 l16ui a4, a2, XT_CPENABLE // a4 = old owner's CPENABLE
144 s16i a4, a2, XT_CPENABLE // update old owner's CPENABLE
150 l16ui a4, a2, XT_CPSTORED // a4 = old owner's CPSTORED
153 s16i a4, a2, XT_CPSTORED // update old owner's CPSTORED
[all …]
Dxtensa_vectors.S141 rsr a2, INTENABLE
144 and a2, a2, a3
145 and a2, a2, a4
146 beqz a2, 9f /* nothing to do */
177 beqz a2, 9f
179 mov a6, a2
182 mov a2, a6
190 extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */
198 add a2, a4, a4 /* a2 = a4 << 1 */
199 addi a2, a2, -1 /* a2 = mask of 1's <= a4 bit */
[all …]
Dxtensa_vectors_xea3.S126 s32si.x4 a2, a15 // Select interrupt, a2 <- (intnum << 2)
174 s32e a2, a1, -48 // [a1-56] <- a2 ; a2 <- EPC
233 s32si.x4 a2, a1 // [a1-80] <- a2 (EPC) ; a2 <- (intnum << 2)
268 l32r a2, .Le1 // Load exc table address
273 addx4 a2, a4, a2 // Index into exc table
274 l32i a4, a2, 0 // Load handler address
276 addi a2, a1, XT_STK_XTRA_SZ // Argument = Exception frame ptr
278 mov a2, a1 // Argument = Exception frame ptr
317 l32e a2, a1, -64 // a2 <- [a1-56]
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/
Dstart.mip189 la a2,init_gpr // Fill register file with set value.
190 jalr a2
192 la a2, set_gpr_boot_values // Fill register file boot info.
193 jalr a2
211 la a2, init_cp0 // Init CP0 Status, Count, Compare, Watch*, and Cause.
212 jalr a2
233 la a2, init_tlb // Generate unique EntryHi contents per entry pair.
234 jalr a2
238 la a2, init_gic // Configure the global interrupt controller.
239 jalr a2
[all …]
Dinit_caches2.mip71 li a2, 2 // Used to test against
72 beq a2, a3, Isets_done // if IS = 2
76 lui a2, 0x8000 // Get a KSeg0 address for cacheops
81 cache 0x8, 0(a2) // Index Store tag Cache opt
84 add a2, v1 // Increment line address by line size
107 li a2, 2 // Used to test against
108 beq a2, a3, Dsets_done // if DS = 2
112 lui a2, 0x8000 // Get a KSeg0 address for cacheops
117 cache 0x9, 0(a2) // Index Store tag Cache opt
120 add a2, v1 // Increment line address by line size
[all …]
/ThreadX-v6.4.1/ports_module/cortex_a7/gnu/example_build/
Dcrt0.S41 mov a2, #0 /* Second arg: fill value */
42 mov fp, a2 /* Null frame pointer */
43 mov r7, a2 /* Null frame pointer for Thumb */
/ThreadX-v6.4.1/ports/arm9/gnu/example_build/
Dcrt0.S26 mov a2, #0 /* Second arg: fill value */
27 mov fp, a2 /* Null frame pointer */
28 mov r7, a2 /* Null frame pointer for Thumb */
/ThreadX-v6.4.1/ports/cortex_r4/gnu/example_build/
Dcrt0.S26 mov a2, #0 /* Second arg: fill value */
27 mov fp, a2 /* Null frame pointer */
28 mov r7, a2 /* Null frame pointer for Thumb */
/ThreadX-v6.4.1/ports/arm11/gnu/example_build/
Dcrt0.S26 mov a2, #0 /* Second arg: fill value */
27 mov fp, a2 /* Null frame pointer */
28 mov r7, a2 /* Null frame pointer for Thumb */
/ThreadX-v6.4.1/ports/cortex_r5/gnu/example_build/
Dcrt0.S26 mov a2, #0 /* Second arg: fill value */
27 mov fp, a2 /* Null frame pointer */
28 mov r7, a2 /* Null frame pointer for Thumb */
/ThreadX-v6.4.1/ports/xtensa/xcc/inc/
Dxtensa_context.h107 XSTRUCT_FIELD (long, 4, XT_STK_A2, a2)
164 XSTRUCT_FIELD (long, 4, XT_STK_A2, a2)
460 s32i a2, a10, 8
511 l32i a2, a9, tx_thread_solicited // a2 = solicited flag
512 beqz a2, 1f
516 addi a2, a1, -XT_STK_XFRM_SZ
517 l32i a3, a2, XT_STK_PC // a3 = return PC
519 movi a2, PS_DI
520 xps a2, a2 // disable interrupts
521 movi a2, 0
[all …]
/ThreadX-v6.4.1/ports/cortex_a15/gnu/example_build/
Dcrt0.S41 mov a2, #0 /* Second arg: fill value */
42 mov fp, a2 /* Null frame pointer */
43 mov r7, a2 /* Null frame pointer for Thumb */
/ThreadX-v6.4.1/ports/cortex_a8/gnu/example_build/
Dcrt0.S41 mov a2, #0 /* Second arg: fill value */
42 mov fp, a2 /* Null frame pointer */
43 mov r7, a2 /* Null frame pointer for Thumb */
/ThreadX-v6.4.1/ports/cortex_a7/gnu/example_build/
Dcrt0.S41 mov a2, #0 /* Second arg: fill value */
42 mov fp, a2 /* Null frame pointer */
43 mov r7, a2 /* Null frame pointer for Thumb */
/ThreadX-v6.4.1/ports/cortex_a9/gnu/example_build/
Dcrt0.S41 mov a2, #0 /* Second arg: fill value */
42 mov fp, a2 /* Null frame pointer */
43 mov r7, a2 /* Null frame pointer for Thumb */
/ThreadX-v6.4.1/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/
Dcrt0.S41 mov a2, #0 /* Second arg: fill value */
42 mov fp, a2 /* Null frame pointer */
43 mov r7, a2 /* Null frame pointer for Thumb */
/ThreadX-v6.4.1/ports/cortex_a5/gnu/example_build/
Dcrt0.S41 mov a2, #0 /* Second arg: fill value */
42 mov fp, a2 /* Null frame pointer */
43 mov r7, a2 /* Null frame pointer for Thumb */

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