Home
last modified time | relevance | path

Searched refs:a1 (Results 1 – 25 of 103) sorted by relevance

12345

/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/example_build/
Dinit_mc_denali.S61 li a1, DENALI_CTL_SECTION
63 lw a0, 0x0c(a1)
65 sw a0, 0x0c(a1)
70 sw a0, 0x04(a1)
72 sw a0, 0x0c(a1)
74 sw a0, 0x10(a1)
76 sw a0, 0x14(a1)
78 sw a0, 0x18(a1)
80 sw a0, 0x1c(a1)
82 sw a0, 0x20(a1)
[all …]
Dinit_gic.S62 la a1, GCR_GIC_STATUS + GCR_CONFIG_ADDR // Read GCR_GIC_STATUS
63 lw a0, 0(a1)
71 li a1, GCR_CONFIG_ADDR + GCR_GIC_BASE // Locate and enable GIC
73 sw a0, 0(a1)
76 li a1, GIC_BASE_ADDR // load GIC KSEG0 Address
77 lw a0, GIC_SH_CONFIG(a1) // GIC_SH_CONFIG
88 sw a0, GIC_SH_RMASK31_0(a1) // (disable 0..31)
89 sw a0, GIC_SH_POL31_0(a1) // (high/rise 24..31)
90 sw a0, GIC_SH_TRIG31_0(a1) // (edge 24..31)
91 sw a0, GIC_SH_SMASK31_00(a1) // (enable 24..31)
[all …]
Dinit_L23caches.S142 ext a1, v0, 0, 4 // extract SA
143 add a1, 1
145 mul a0, a0, a1 // Get total number of sets
182 ext a1, v0, CFG2_TASHIFT, 4 // Extrace L3 associativity 2TA encoding
183 add a1, 1 // Decode L3 associativity (number of sets)
184 mul a0, a0, a1 // Compute total number of sets
Dset_gpr_boot_values.S117 la a1, GCR_CONFIG_ADDR // KSEG1(GCRBASE)
118 lw a0, GCR_BASE(a1) // read GCR_BASE
119 ins a1, $0, 29, 3 // Convert KSEG1 to physical address.
121 beq a1, a0, gcr_found
Dinit_caches2.S171 ext a1, v0, 0, 4 // extract ways encoding
172 add a1, 1 // Decode L2 number of ways
174 mul a3, a3, a1 // Get total number of sets (sets per way * number of ways)
210 ext a1, v0, CFG2_TASHIFT, 4 // Extrace L3 associativity 2TA encoding
211 add a1, 1 // Decode L3 associativity (number of sets)
212 mul a3, a3, a1 // Compute total number of sets
Dstart.S258 li a1, 0xf
259 ins a2, a1, 29, 1 // changed to KSEG1 address by setting bit 29
413 la a1, main
414 mtc0 a1, C0_ERRPC // ErrorEPC
425 move a1, r8_core_num // main(arg1) is the core number.
446 ll a0, 0(a1)
448 sc a0, 0(a1) // Attempt atomic potato++
/ThreadX-v6.4.1/ports/xtensa/xcc/src/
Dxtensa_vectors_xea3.S131 addi a1, a1, -XT_STK_XTRA_SZ // Adjust for extra save area
138 s32si.x4 a10, a1 // Select interrupt, a10 <- (intnum << 2)
141 s32stk a9, a1, 96 // Set new stack pointer
158 l32e a8, a1, -64 // a8 <- [a1-32]
159 l32e a9, a1, -64 // a9 <- [a1-28]
160 l32e a10, a1, -64 // a10 <- [a1-24]
161 l32e a11, a1, -64 // a11 <- [a1-20]
162 l32e a12, a1, -64 // a12 <- [a1-16]
163 l32e a13, a1, -64 // a13 <- [a1-12]
164 l32e a14, a1, -64 // a14 <- [a1-8]
[all …]
Dxtensa_coproc_handler.S477 addi a1, a1, -16 // reserve 16 bytes on stack
478 s32i a0, a1, 0 // save return address
479 s32i a15, a1, 8 // must save a15 (see dispatch)
485 l32i a0, a1, 0 // restore return address
486 l32i a15, a1, 8 // restore a15
487 addi a1, a1, 16
490 entry a1, 48 // reserve 16 bytes on stack
491 s32i a0, a1, 0 // save return address
497 l32i a0, a1, 0 // restore return address
573 addi a1, a1, XT_STK_FRMSZ // deallocate stack frame
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/
Dinit_mc_denali.mip61 li a1, DENALI_CTL_SECTION
63 lw a0, 0x0c(a1)
65 sw a0, 0x0c(a1)
70 sw a0, 0x04(a1)
72 sw a0, 0x0c(a1)
74 sw a0, 0x10(a1)
76 sw a0, 0x14(a1)
78 sw a0, 0x18(a1)
80 sw a0, 0x1c(a1)
82 sw a0, 0x20(a1)
[all …]
Dinit_gic.mip62 la a1, GCR_GIC_STATUS + GCR_CONFIG_ADDR // Read GCR_GIC_STATUS
63 lw a0, 0(a1)
71 li a1, GCR_CONFIG_ADDR + GCR_GIC_BASE // Locate and enable GIC
73 sw a0, 0(a1)
76 li a1, GIC_BASE_ADDR // load GIC KSEG0 Address
77 lw a0, GIC_SH_CONFIG(a1) // GIC_SH_CONFIG
88 sw a0, GIC_SH_RMASK31_0(a1) // (disable 0..31)
89 sw a0, GIC_SH_POL31_0(a1) // (high/rise 24..31)
90 sw a0, GIC_SH_TRIG31_0(a1) // (edge 24..31)
91 sw a0, GIC_SH_SMASK31_00(a1) // (enable 24..31)
[all …]
/ThreadX-v6.4.1/ports/xtensa/xcc/inc/
Dxtensa_context.h106 XSTRUCT_FIELD (long, 4, XT_STK_A1, a1) /* stack pointer before interrupt */
163 XSTRUCT_FIELD (long, 4, XT_STK_A1, a1)
427 addi a10, a1, -XT_STK_FRMSZ
445 addi a10, a1, -XT_STK_FRMSZ + XT_STK_ALIGN_SZ // where to save
458 addi a10, a1, -XT_STK_FRMSZ -32
499 l32i a1, a9, tx_thread_stack_ptr // SP = _tx_thread_execute_ptr->tx_thread_stack_ptr
515 addi a1, a1, XT_STK_FRMSZ // restore original SP
516 addi a2, a1, -XT_STK_XFRM_SZ
529 addi a10, a1, XT_STK_ALIGN_SZ // where to restore from
539 addi a8, a1, -32
[all …]
/ThreadX-v6.4.1/ports_module/cortex_a7/gnu/example_build/
Dcrt0.S45 ldr a1, .LC1 /* First arg: start of memory block */
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/arm9/gnu/example_build/
Dcrt0.S30 ldr a1, .LC1 /* First arg: start of memory block */
32 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_r4/gnu/example_build/
Dcrt0.S30 ldr a1, .LC1 /* First arg: start of memory block */
32 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/arm11/gnu/example_build/
Dcrt0.S30 ldr a1, .LC1 /* First arg: start of memory block */
32 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_r5/gnu/example_build/
Dcrt0.S30 ldr a1, .LC1 /* First arg: start of memory block */
32 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_a15/gnu/example_build/
Dcrt0.S45 ldr a1, .LC1 /* First arg: start of memory block */
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_a8/gnu/example_build/
Dcrt0.S45 ldr a1, .LC1 /* First arg: start of memory block */
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_a7/gnu/example_build/
Dcrt0.S45 ldr a1, .LC1 /* First arg: start of memory block */
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_a9/gnu/example_build/
Dcrt0.S45 ldr a1, .LC1 /* First arg: start of memory block */
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/
Dcrt0.S45 ldr a1, .LC1 /* First arg: start of memory block */
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_a5/gnu/example_build/
Dcrt0.S45 ldr a1, .LC1 /* First arg: start of memory block */
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_a17/gnu/example_build/
Dcrt0.S45 ldr a1, .LC1 /* First arg: start of memory block */
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_a12/gnu/example_build/
Dcrt0.S45 ldr a1, .LC1 /* First arg: start of memory block */
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/risc-v32/iar/src/
Dtx_thread_stack_build.s188 sw x0, 104(t0) ; Initial a1
191 sw a1, 120(t0) ; Initial mepc
225 …csrr a1, fcsr ; Read fcsr and use it for initial value for e…
226 sw a1, 252(t0) ; Initial fscr

12345