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/ThreadX-v6.4.1/ports/xtensa/xcc/src/
Dtx_xtensa_stack_error_handler.c100 register int32_t sc __asm__ ("a2") = SYS_log_msg; in _tx_xtensa_stack_error_handler()
101 register char * msg __asm__ ("a3") in _tx_xtensa_stack_error_handler()
103 register TX_THREAD * thd __asm__ ("a4") = thread; in _tx_xtensa_stack_error_handler()
104 __asm__ volatile ("simcall" :: "a" (sc), "a" (msg), "a" (thd) ); in _tx_xtensa_stack_error_handler()
117 __asm__ volatile ("simcall"); /* control to debugger or exit */ in _tx_xtensa_stack_error_handler()
119 __asm__ volatile ("break 1, 15"); /* control to debugger or panic */ in _tx_xtensa_stack_error_handler()
/ThreadX-v6.4.1/ports/cortex_m3/ac5/inc/
Dtx_port.h89 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
314 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
320 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
323 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
337 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
344 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
488 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
532 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
533 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
548 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports/cortex_m4/ac5/inc/
Dtx_port.h89 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
314 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
320 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
323 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
337 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
344 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
488 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
532 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
533 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
548 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports/cortex_m4/ac6/inc/
Dtx_port.h89 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
314 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
320 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
323 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
337 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
344 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
488 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
532 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
533 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
548 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports/cortex_m7/ac5/inc/
Dtx_port.h89 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
314 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
320 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
323 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
337 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
344 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
488 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
532 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
533 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
548 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports/cortex_m7/gnu/inc/
Dtx_port.h89 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
314 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
320 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
323 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
337 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
344 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
488 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
532 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
533 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
548 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports/cortex_m7/ac6/inc/
Dtx_port.h89 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
314 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
320 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
323 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
337 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
344 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
488 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
532 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
533 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
548 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports/cortex_m7/iar/inc/
Dtx_port.h89 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
314 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
320 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
323 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
337 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
344 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
488 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
532 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
533 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
548 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports/cortex_m3/ac6/inc/
Dtx_port.h89 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
314 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
320 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
323 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
337 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
344 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
488 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
532 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
533 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
548 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports/cortex_m3/gnu/inc/
Dtx_port.h89 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
314 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
320 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
323 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
337 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
344 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
488 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
532 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
533 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
548 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports/cortex_m3/keil/inc/
Dtx_port.h89 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
314 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
320 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
323 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
337 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
344 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
488 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
532 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
533 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
548 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports/cortex_m3/iar/inc/
Dtx_port.h89 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
314 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
320 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
323 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
337 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
344 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
488 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
532 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
533 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
548 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports_arch/ARMv7-M/threadx/inc/
Dtx_port.h89 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
314 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
320 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
323 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
337 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
344 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
488 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
532 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
533 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
548 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports/cortex_m4/gnu/inc/
Dtx_port.h89 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
314 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
320 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
323 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
337 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
344 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
488 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
532 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
533 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
548 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports/cortex_m4/iar/inc/
Dtx_port.h89 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
314 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
320 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
323 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
337 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
344 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
488 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
532 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
533 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
548 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports/cortex_m4/keil/inc/
Dtx_port.h89 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
314 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
320 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
323 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
337 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
344 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
488 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
532 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
533 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
548 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m4/ac5/inc/
Dtx_port.h78 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
319 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
325 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
328 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
342 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
349 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
493 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
537 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
538 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
555 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m4/gnu/inc/
Dtx_port.h78 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
319 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
325 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
328 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
342 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
349 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
493 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
537 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
538 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
555 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m3/ac6/inc/
Dtx_port.h78 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
319 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
325 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
328 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
342 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
349 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
493 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
537 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
538 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
555 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m3/gnu/inc/
Dtx_port.h78 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
319 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
325 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
328 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
342 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
349 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
493 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
537 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
538 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
555 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m7/gnu/inc/
Dtx_port.h78 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
319 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
325 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
328 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
342 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
349 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
493 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
537 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
538 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
555 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m7/iar/inc/
Dtx_port.h78 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
319 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
325 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
328 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
342 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
349 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
493 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
537 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
538 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
555 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m7/ac5/inc/
Dtx_port.h78 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
319 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
325 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
328 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
342 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
349 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
493 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
537 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
538 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
555 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m7/ac6/inc/
Dtx_port.h78 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
319 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
325 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
328 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
342 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
349 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
493 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
537 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
538 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
555 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m4/ac6/inc/
Dtx_port.h78 #define __asm__ __asm /* Define to make all inline asm look similar */ macro
319 __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); in __get_control_value()
325 __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); in __set_control_value()
328 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
342 __asm__ volatile ("MSR CONTROL,control_value"); in __set_control_value()
349 #define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0");
493 __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); in __get_ipsr_value()
537 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m…
538 … __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) );
555 __asm__ volatile ("MRS %0, BASEPRI ": "=r" (posture)); in __get_interrupt_posture()
[all …]

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