Home
last modified time | relevance | path

Searched refs:SVC_MODE_BITS (Results 1 – 25 of 25) sorted by relevance

/ThreadX-v6.4.1/ports/arm11/iar/src/
Dtx_thread_context_restore.s42 SVC_MODE_BITS DEFINE 0x13 ; SVC mode value label
239 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
Dtx_thread_fiq_context_restore.s44 SVC_MODE_BITS DEFINE 0x13 ; SVC mode value label
249 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
/ThreadX-v6.4.1/ports/arm9/ac5/src/
Dtx_thread_context_restore.s42 SVC_MODE_BITS EQU 0x13 ; SVC mode value define
240 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
Dtx_thread_fiq_context_restore.s43 SVC_MODE_BITS EQU 0x13 ; SVC mode value define
251 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
/ThreadX-v6.4.1/ports/arm9/iar/src/
Dtx_thread_context_restore.s41 SVC_MODE_BITS DEFINE 0x13 ; SVC mode value label
237 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
Dtx_thread_fiq_context_restore.s43 SVC_MODE_BITS DEFINE 0x13 ; SVC mode value label
248 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
/ThreadX-v6.4.1/ports/arm11/ac5/src/
Dtx_thread_context_restore.s42 SVC_MODE_BITS EQU 0x13 ; SVC mode value define
240 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
Dtx_thread_fiq_context_restore.s43 SVC_MODE_BITS EQU 0x13 ; SVC mode value define
251 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
/ThreadX-v6.4.1/ports/cortex_a9/iar/src/
Dtx_thread_context_restore.s41 SVC_MODE_BITS DEFINE 0x13 ; SVC mode value label
254 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
Dtx_thread_fiq_context_restore.s43 SVC_MODE_BITS DEFINE 0x13 ; SVC mode value label
264 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
/ThreadX-v6.4.1/ports/cortex_a5/iar/src/
Dtx_thread_context_restore.s41 SVC_MODE_BITS DEFINE 0x13 ; SVC mode value label
256 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
Dtx_thread_fiq_context_restore.s43 SVC_MODE_BITS DEFINE 0x13 ; SVC mode value label
266 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
/ThreadX-v6.4.1/ports/arm9/gnu/src/
Dtx_thread_fiq_context_restore.S31 SVC_MODE_BITS = 0x13 @ SVC mode value define
245 ORR r3, r3, #SVC_MODE_BITS @ Or-in new interrupt lockout bit
/ThreadX-v6.4.1/ports/arm11/gnu/src/
Dtx_thread_fiq_context_restore.S31 SVC_MODE_BITS = 0x13 @ SVC mode value define
245 ORR r3, r3, #SVC_MODE_BITS @ Or-in new interrupt lockout bit
/ThreadX-v6.4.1/ports/cortex_a7/iar/src/
Dtx_thread_context_restore.s41 SVC_MODE_BITS DEFINE 0x13 ; SVC mode value label
254 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
Dtx_thread_fiq_context_restore.s43 SVC_MODE_BITS DEFINE 0x13 ; SVC mode value label
264 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
/ThreadX-v6.4.1/ports/cortex_a8/iar/src/
Dtx_thread_context_restore.s41 SVC_MODE_BITS DEFINE 0x13 ; SVC mode value label
254 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
Dtx_thread_fiq_context_restore.s43 SVC_MODE_BITS DEFINE 0x13 ; SVC mode value label
264 ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit
/ThreadX-v6.4.1/ports/cortex_r7/ghs/src/
Dtx_thread_fiq_nesting_end.arm39 SVC_MODE_BITS = 0x13 # SVC mode value */
/ThreadX-v6.4.1/ports/cortex_r5/ghs/src/
Dtx_thread_fiq_nesting_end.arm39 SVC_MODE_BITS = 0x13 # SVC mode value */
/ThreadX-v6.4.1/ports/cortex_a8/ghs/src/
Dtx_thread_fiq_nesting_end.arm39 SVC_MODE_BITS = 0x13 # SVC mode value */
/ThreadX-v6.4.1/ports/cortex_a5/ghs/src/
Dtx_thread_fiq_nesting_end.arm39 SVC_MODE_BITS = 0x13 # SVC mode value */
/ThreadX-v6.4.1/ports/cortex_a9/ghs/src/
Dtx_thread_fiq_nesting_end.arm39 SVC_MODE_BITS = 0x13 # SVC mode value */
/ThreadX-v6.4.1/ports/cortex_a7/ghs/src/
Dtx_thread_fiq_nesting_end.arm39 SVC_MODE_BITS = 0x13 # SVC mode value */
/ThreadX-v6.4.1/ports/cortex_r4/ghs/src/
Dtx_thread_fiq_nesting_end.arm39 SVC_MODE_BITS = 0x13 # SVC mode value */