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/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/src/
Dtx_thread_smp_initialize_wait.S24 #define INITIAL_SR 0xFF00 /* All IM bits set */ macro
106 ori $8, $8, INITIAL_SR # Build initial SR
Dtx_initialize_low_level.S25 INITIAL_SR = 0xFF00 # All IM bits set define
88 ori $8, $8, INITIAL_SR # Build initial SR
Dtx_thread_stack_build.S23 INITIAL_SR = 0xFF03 # Interrupt enable previous define
191 ori $9, $9, INITIAL_SR # Build initial SR
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/src/
Dtx_thread_smp_initialize_wait.mip24 #define INITIAL_SR 0xFF00 /* All IM bits set */
106 ori $8, $8, INITIAL_SR # Build initial SR
Dtx_thread_stack_build.mip23 INITIAL_SR = 0xFF03 # Interrupt enable previous
195 ori $9, $9, INITIAL_SR # Build initial SR
Dtx_initialize_low_level.mip25 INITIAL_SR = 0xFF00 # All IM bits set
88 ori $8, $8, INITIAL_SR # Build initial SR