Home
last modified time | relevance | path

Searched refs:GIC_CPU_REG (Results 1 – 1 of 1) sorted by relevance

/ThreadX-v6.4.1/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/
Dtx_zynqmp_low_level.c54 #define GIC_CPU_REG(offset) *((volatile uint32_t *)(GIC_CPU_BASEADDR+offset)) macro
56 #define GICC_CTLR GIC_CPU_REG(0x000)
57 #define GICC_PMR GIC_CPU_REG(0x004)
58 #define GICC_IAR GIC_CPU_REG(0x00c)
59 #define GICC_EOIR GIC_CPU_REG(0x010)