| /ThreadX-v6.4.1/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_module/cortex_a35/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports/cortex_a76/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
| /ThreadX-v6.4.1/ports/cortex_a76/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 43 volatile uint32_t GICD_ISENABLER[32]; // +0x0100 member
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
|
