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Searched refs:GICD_CTLR (Results 1 – 25 of 138) sorted by relevance

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/ThreadX-v6.4.1/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_module/cortex_a35/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_module/cortex_a35/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports/cortex_a75/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports/cortex_a76/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports/cortex_a76ae/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports/cortex_a65ae/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.4.1/ports/cortex_a77/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()

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