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Searched refs:GCR_REG5_BASE (Results 1 – 2 of 2) sorted by relevance

/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/
Dcps.h237 #define GCR_REG5_BASE 0x01A0 macro
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/example_build/
Dcps.h237 #define GCR_REG5_BASE 0x01A0 macro