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Searched refs:GCR_CO_RESET_BASE (Results 1 – 3 of 3) sorted by relevance

/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/
Dcps.h312 #define GCR_CO_RESET_BASE 0x0020 macro
Dstart.mip164 /* (with vaddr[12..0] = 0 for alignment with GCR_CO_RESET_BASE). */
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/example_build/
Dcps.h312 #define GCR_CO_RESET_BASE 0x0020 macro