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Searched refs:FIQEnable (Results 1 – 2 of 2) sorted by relevance

/ThreadX-v6.4.1/ports/arm9/ac5/example_build/
Dtx_initialize_low_level.s56 FIQEnable EQU 0x0a000108 ; FIQ Enable Set Register define
/ThreadX-v6.4.1/ports/arm11/ac5/example_build/
Dtx_initialize_low_level.s56 FIQEnable EQU 0x0a000108 ; FIQ Enable Set Register define