| /ThreadX-v6.4.1/ports/arm9/iar/src/ |
| D | tx_thread_schedule.s | 33 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
35 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
98 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/arm11/iar/src/ |
| D | tx_thread_schedule.s | 33 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
35 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
98 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/arm9/ac5/src/ |
| D | tx_thread_schedule.s | 34 ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask define
36 ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask define
99 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/arm11/ac5/src/ |
| D | tx_thread_schedule.s | 34 ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask define
36 ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask define
99 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/arm11/gnu/src/ |
| D | tx_thread_schedule.S | 26 ENABLE_INTS = 0xC0 @ IRQ & FIQ Interrupts enabled mask define
28 ENABLE_INTS = 0x80 @ IRQ Interrupts enabled mask define
111 BIC r0, r2, #ENABLE_INTS @ Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/arm9/gnu/src/ |
| D | tx_thread_schedule.S | 26 ENABLE_INTS = 0xC0 @ IRQ & FIQ Interrupts enabled mask define
28 ENABLE_INTS = 0x80 @ IRQ Interrupts enabled mask define
111 BIC r0, r2, #ENABLE_INTS @ Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/cortex_a9/iar/src/ |
| D | tx_thread_schedule.s | 33 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
35 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
101 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/cortex_a5/iar/src/ |
| D | tx_thread_schedule.s | 33 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
35 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
101 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/cortex_a7/iar/src/ |
| D | tx_thread_schedule.s | 33 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
35 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
101 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/cortex_a8/iar/src/ |
| D | tx_thread_schedule.s | 33 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
35 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
101 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/cortex_r4/ghs/src/ |
| D | tx_thread_schedule.arm | 33 ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask
35 ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask
90 BIC r0, r2, ENABLE_INTS # Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/cortex_r7/ghs/src/ |
| D | tx_thread_schedule.arm | 33 ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask
35 ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask
90 BIC r0, r2, ENABLE_INTS # Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/cortex_a7/ghs/src/ |
| D | tx_thread_schedule.arm | 33 ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask
35 ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask
90 BIC r0, r2, ENABLE_INTS # Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/cortex_r5/ghs/src/ |
| D | tx_thread_schedule.arm | 33 ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask
35 ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask
90 BIC r0, r2, ENABLE_INTS # Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/cortex_a8/ghs/src/ |
| D | tx_thread_schedule.arm | 33 ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask
35 ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask
90 BIC r0, r2, ENABLE_INTS # Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/cortex_a9/ghs/src/ |
| D | tx_thread_schedule.arm | 33 ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask
35 ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask
90 BIC r0, r2, ENABLE_INTS # Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports/cortex_a5/ghs/src/ |
| D | tx_thread_schedule.arm | 33 ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask
35 ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask
90 BIC r0, r2, ENABLE_INTS # Clear the disable bit(s)
|
| /ThreadX-v6.4.1/ports_module/cortex_a7/ac5/module_manager/src/ |
| D | tx_thread_schedule.s | 46 ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask define
48 ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask define
270 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
|
