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Searched refs:DDR_1_REG (Results 1 – 1 of 1) sorted by relevance

/ThreadX-v6.4.1/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/
Dtx_zynqmp_low_level.c201 #define DDR_1_REG (DDR_1_SIZE/0x40000000) in mmu_tbl_init() macro
202 for (; i < (0x020 + DDR_1_REG); i++, sect += 0x40000000) { in mmu_tbl_init()
205 #if DDR_1_REG < 0x20 in mmu_tbl_init()