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Searched refs:CPSR_MASK (Results 1 – 25 of 62) sorted by relevance

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/ThreadX-v6.4.1/ports_module/cortex_r4/ac6/module_manager/src/
Dtx_thread_stack_build.S36 #define CPSR_MASK 0xDF // Mask initial CPSR, IRQ & FIQ ints enabled macro
38 #define CPSR_MASK 0x9F // Mask initial CPSR, IRQ ints enabled macro
148 BIC r3, r3, #CPSR_MASK // Mask mode bits of CPSR
Dtxm_module_manager_thread_stack_build.S26 #define CPSR_MASK 0xBF // Mask initial CPSR, IRQ ints enabled macro
131 BIC r3, r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports_module/cortex_a7/gnu/module_manager/src/
Dtx_thread_stack_build.s35 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
37 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
131 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
Dtxm_module_manager_thread_stack_build.s33 #define CPSR_MASK 0xDF // Mask initial CPSR, IRQ & FIQ ints enabled macro
35 #define CPSR_MASK 0x9F // Mask initial CPSR, IRQ ints enabled macro
147 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/cortex_a9/gnu/src/
Dtx_thread_stack_build.S37 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
39 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
134 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/cortex_a9/ac6/src/
Dtx_thread_stack_build.S37 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
39 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
134 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/cortex_a12/ac6/src/
Dtx_thread_stack_build.S37 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
39 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
134 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/cortex_a12/gnu/src/
Dtx_thread_stack_build.S37 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
39 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
134 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/cortex_a5/ac6/src/
Dtx_thread_stack_build.S37 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
39 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
134 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/cortex_a7/gnu/src/
Dtx_thread_stack_build.S37 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
39 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
134 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/cortex_a15/ac6/src/
Dtx_thread_stack_build.S37 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
39 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
134 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/cortex_a8/ac6/src/
Dtx_thread_stack_build.S37 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
39 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
134 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/cortex_a17/gnu/src/
Dtx_thread_stack_build.S37 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
39 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
134 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/cortex_a15/gnu/src/
Dtx_thread_stack_build.S37 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
39 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
134 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/cortex_a17/ac6/src/
Dtx_thread_stack_build.S37 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
39 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
134 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports_arch/ARMv7-A/threadx/common/src/
Dtx_thread_stack_build.S37 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
39 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
134 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/cortex_a7/ac6/src/
Dtx_thread_stack_build.S37 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
39 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
134 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/cortex_a8/gnu/src/
Dtx_thread_stack_build.S37 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
39 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
134 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/cortex_a5/gnu/src/
Dtx_thread_stack_build.S37 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
39 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
134 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/cortex_r4/ac6/src/
Dtx_thread_stack_build.S34 #define CPSR_MASK 0xDF // Mask initial CPSR, IRQ & FIQ ints enabled macro
36 #define CPSR_MASK 0x9F // Mask initial CPSR, IRQ ints enabled macro
149 BIC r3, r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports_smp/cortex_r8_smp/ac5/src/
Dtx_thread_stack_build.s24 CPSR_MASK EQU 0xDF // Mask initial CPSR, IRQ & FIQ ints enabled define
26 CPSR_MASK EQU 0x9F // Mask initial CPSR, IRQ ints enabled define
131 BIC r3, r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.4.1/ports_module/cortex_a7/iar/module_manager/src/
Dtxm_module_manager_thread_stack_build.s27 CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled define
29 CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled define
/ThreadX-v6.4.1/ports_module/cortex_a7/ac5/module_manager/src/
Dtxm_module_manager_thread_stack_build.s36 CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled define
38 CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled define
/ThreadX-v6.4.1/ports/cortex_a9/iar/src/
Dtx_thread_stack_build.s34 CPSR_MASK DEFINE 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled label
36 CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled label
141 BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR
/ThreadX-v6.4.1/ports/arm11/iar/src/
Dtx_thread_stack_build.s34 CPSR_MASK DEFINE 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled label
36 CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled label
141 BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR

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