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Searched refs:CORE_OTHER_CONTROL_BLOCK (Results 1 – 4 of 4) sorted by relevance

/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/example_build/
Djoin_domain.S77 lw a0, (CORE_OTHER_CONTROL_BLOCK | GCR_CO_COHERENCE)(r22_gcr_addr) // GCR_CO_COHERENCE
Dcps.h288 #define CORE_OTHER_CONTROL_BLOCK 0x4000 macro
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/
Djoin_domain.mip77 lw a0, (CORE_OTHER_CONTROL_BLOCK | GCR_CO_COHERENCE)(r22_gcr_addr) // GCR_CO_COHERENCE
Dcps.h288 #define CORE_OTHER_CONTROL_BLOCK 0x4000 macro