1 /******************************************************************************
2 	TMS320C66xx KeyStone Multicore DSP Software Development Kit (SDK). Rev 2A.
3 	(C) MicroLAB Systems, 2014-2015
4 
5 	File:	Macros
6 	-----
7 
8 	Notes:
9 	------
10 	1.	This C-header file contains C66xx DSP macro definitions and
11 		is used with C66XX.h C-header file.
12 
13 	2.	This file is best viewed with the TAB setting set to '4'.
14 
15 ******************************************************************************/
16 
17 
18 /**
19  * @file  C66XX_MACROS.hxx
20  *
21  * @brief  Macros
22  *
23  * This file contains C66xx DSP macro definitions
24  *
25  */
26 
27 
28 #ifndef __C66XX_MACROS_HXX__								// check for this file has been already included
29 #define __C66XX_MACROS_HXX__								1
30 
31 
32 //=============================================================================
33 //------------ I/O peripherals data type selector for C66xx DSP ---------------
34 // C66xx DSP has all I/O peripherals aligned as LSB of 32-bit words, then
35 // I/O peripherals should be accessed as UNSIGNED only.
36 
37 // The declared __C66XX_IO_DATA_TYPE__ is used to unify below macros and
38 // functions and to make particular selection at the run-time compilation time.
39 //================================================================
40 
41 typedef volatile uint32_t									__C66XX_IO_DATA_TYPE__;
42 
43 // read-back data bitmask for DSP memory-mapped registers (32-bit wide)
44 #define C66XX_RG_DATA_BITMASK								0xffffffff
45 //=============================================================================
46 
47 
48 
49 //=============================================================================
50 //============ General register access macros =================================
51 //=============================================================================
52 // Macro to get selected register value
53 #define C66XX_GET_RG_VALUE(addr)							((*(__C66XX_IO_DATA_TYPE__ *) addr) & C66XX_RG_DATA_BITMASK)
54 
55 // Macro to set selected register to value
56 #define C66XX_SET_RG_VALUE(addr, val)						((*(__C66XX_IO_DATA_TYPE__ *) addr) = (val & C66XX_RG_DATA_BITMASK))
57 
58 // Macro to make FIELD for the supplied value
59 #define C66XX_MAKE_FIELD(FIELD, val)						(((val) << C66XX_##FIELD##_BITSHIFT) & C66XX_##FIELD##_BITMASK)
60 
61 // Macro to get FIELD value from the selected register
62 #define C66XX_GET_FIELD_VALUE(addr, FIELD)					(((*(__C66XX_IO_DATA_TYPE__ *) addr) & C66XX_##FIELD##_BITMASK) >> C66XX_##FIELD##_BITSHIFT)
63 
64 // Macro to set FIELD to value in the selected register
65 #define C66XX_SET_FIELD_VALUE(addr, FIELD, val)				((*(__C66XX_IO_DATA_TYPE__ *) addr) = ((*(__C66XX_IO_DATA_TYPE__ *) addr) & ~C66XX_##FIELD##_BITMASK) | C66XX_MAKE_FIELD(FIELD, val))
66 
67 //=============================================================================
68 
69 
70 
71 //=============================================================================
72 //============ DSP core registers macros ======================================
73 //=============================================================================
74 
75 //------------ DSP CorePack revision register macros --------------------------
76 #define C66XX_get_core_mm_revid_rg()						C66XX_GET_RG_VALUE(C66XX_CORE_MM_REVID_RG_ADDR)
77 
78 	// dedicated bit specific macros
79 #define C66XX_get_core_mm_revid_version()					C66XX_GET_FIELD_VALUE(C66XX_CORE_MM_REVID_RG_ADDR, CORE_MM_REVID_VERSION)
80 #define C66XX_get_core_mm_revid_revision()					C66XX_GET_FIELD_VALUE(C66XX_CORE_MM_REVID_RG_ADDR, CORE_MM_REVID_REVISION)
81 
82 	// condition check macros (for use in IF() and other conditional operators)
83 #define C66XX_CORE_MM_REVID_VERSION_IS_C6678				(C66XX_get_core_mm_revid_version() == C66XX_CORE_MM_REVID_VERSION_C6678)
84 #define C66XX_CORE_MM_REVID_REVISION_IS_1_0					(C66XX_get_core_mm_revid_revision() == C66XX_CORE_MM_REVID_REVISION_1_0)
85 #define C66XX_CORE_MM_REVID_REVISION_IS_2_0					(C66XX_get_core_mm_revid_revision() == C66XX_CORE_MM_REVID_REVISION_2_0)
86 
87 //------------ DSP interrupt controller registers macros ----------------------
88 // i index corresonds to DSP Event registers number
89 // Note that i index should be from 0 to 3 !!!
90 #define C66XX_get_core_evtflag_rg_addr(i)					(C66XX_CORE_EVTFLAG_RG_BADDR + i * C66XX_CORE_EVTFLAG_RG_OFFSET)
91 #define C66XX_get_core_evtflag_rg(i)						C66XX_GET_RG_VALUE(C66XX_get_core_evtflag_rg_addr(i))
92 
93 #define C66XX_get_core_evtset_rg_addr(i)					(C66XX_CORE_EVTSET_RG_BADDR + i * C66XX_CORE_EVTSET_RG_OFFSET)
94 #define C66XX_set_core_evtset_rg(i, v)						C66XX_SET_RG_VALUE(C66XX_get_core_evtset_rg_addr(i), v)
95 
96 #define C66XX_get_core_evtclr_rg_addr(i)					(C66XX_CORE_EVTCLR_RG_BADDR + i * C66XX_CORE_EVTCLR_RG_OFFSET)
97 #define C66XX_set_core_evtclr_rg(i, v)						C66XX_SET_RG_VALUE(C66XX_get_core_evtclr_rg_addr(i), v)
98 
99 #define C66XX_get_core_evtmask_rg_addr(i)					(C66XX_CORE_EVTMASK_RG_BADDR + i * C66XX_CORE_EVTMASK_RG_OFFSET)
100 #define C66XX_get_core_evtmask_rg(i)						C66XX_GET_RG_VALUE(C66XX_get_core_evtmask_rg_addr(i))
101 #define C66XX_set_core_evtmask_rg(i, v)						C66XX_SET_RG_VALUE(C66XX_get_core_evtmask_rg_addr(i), v)
102 
103 //------------ DSP interrupt macros -------------------------------------------
104 // These macros are used to set/get particular DSP Event in DSP Event registers
105 // i index corresonds to DSP Event ID number (0 - 127)
106 #define C66XX_get_core_event_id_rg(i)						(i / 32)
107 #define C66XX_get_core_event_id_bitmask(i)					(0x1 << (i % 32))
108 
109 #define C66XX_get_core_event_id_flag(i)						(C66XX_get_core_evtflag_rg(C66XX_get_core_event_id_rg(i)) & C66XX_get_core_event_id_bitmask(i))
110 #define C66XX_set_core_event_id_flag(i)						(C66XX_set_core_evtset_rg(C66XX_get_core_event_id_rg(i), C66XX_get_core_event_id_bitmask(i)))
111 #define C66XX_clear_core_event_id_flag(i)					(C66XX_set_core_evtclr_rg(C66XX_get_core_event_id_rg(i), C66XX_get_core_event_id_bitmask(i)))
112 #define C66XX_get_core_event_id_mask(i)						(C66XX_get_core_evtmask_rg(C66XX_get_core_event_id_rg(i)) & C66XX_get_core_event_id_bitmask(i))
113 #define C66XX_set_core_event_id_mask(i)						(C66XX_set_core_evtmask_rg(C66XX_get_core_event_id_rg(i), C66XX_get_core_event_id_bitmask(i)))
114 
115 //=============================================================================
116 
117 
118 
119 //=============================================================================
120 //============ PLL controller registers macros ================================
121 //=============================================================================
122 
123 //------------ PLL control register macros ------------------------------------
124 #define C66XX_get_pll_pllctl_rg()							C66XX_GET_RG_VALUE(C66XX_PLL_PLLCTL_RG_ADDR)
125 #define C66XX_set_pll_pllctl_rg(v)							C66XX_SET_RG_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, v)
126 
127 	// dedicated bit specific macros
128 #define C66XX_get_pll_pllctl_pllensrc()						C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLENSRC)
129 #define C66XX_set_pll_pllctl_pllensrc(v)					C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLENSRC, v)
130 #define C66XX_get_pll_pllctl_pllrst()						C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLRST)
131 #define C66XX_set_pll_pllctl_pllrst(v)						C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLRST, v)
132 #define C66XX_get_pll_pllctl_pllpwrdn()						C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLPWRDN)
133 #define C66XX_set_pll_pllctl_pllpwrdn(v)					C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLPWRDN, v)
134 #define C66XX_get_pll_pllctl_pllen()						C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLEN)
135 #define C66XX_set_pll_pllctl_pllen(v)						C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLEN, v)
136 
137 	// direct bit set macros
138 #define C66XX_SET_PLL_PLLCTL_PLLENSRC_ON					C66XX_set_pll_pllctl_pllensrc(C66XX_ON)
139 #define C66XX_SET_PLL_PLLCTL_PLLENSRC_OFF					C66XX_set_pll_pllctl_pllensrc(C66XX_OFF)
140 #define C66XX_SET_PLL_PLLCTL_PLLRST_ON						C66XX_set_pll_pllctl_pllrst(C66XX_ON)
141 #define C66XX_SET_PLL_PLLCTL_PLLRST_OFF						C66XX_set_pll_pllctl_pllrst(C66XX_OFF)
142 #define C66XX_SET_PLL_PLLCTL_PLLPWRDN_ON					C66XX_set_pll_pllctl_pllpwrdn(C66XX_ON)
143 #define C66XX_SET_PLL_PLLCTL_PLLPWRDN_OFF					C66XX_set_pll_pllctl_pllpwrdn(C66XX_OFF)
144 #define C66XX_SET_PLL_PLLCTL_PLLEN_ON						C66XX_set_pll_pllctl_pllen(C66XX_ON)
145 #define C66XX_SET_PLL_PLLCTL_PLLEN_OFF						C66XX_set_pll_pllctl_pllen(C66XX_OFF)
146 
147 	// condition check macros (for use in IF() and other conditional operators)
148 #define C66XX_PLL_PLLCTL_PLLENSRC_IS_ON						(C66XX_get_pll_pllctl_pllensrc() == C66XX_ON)
149 #define C66XX_PLL_PLLCTL_PLLRST_IS_ON						(C66XX_get_pll_pllctl_pllrst() == C66XX_ON)
150 #define C66XX_PLL_PLLCTL_PLLPWRDN_IS_ON						(C66XX_get_pll_pllctl_pllpwrdn() == C66XX_ON)
151 #define C66XX_PLL_PLLCTL_PLLEN_IS_ON						(C66XX_get_pll_pllctl_pllen() == C66XX_ON)
152 
153 
154 //------------ PLL secondary control register macros --------------------------
155 #define C66XX_get_pll_secctl_rg()							C66XX_GET_RG_VALUE(C66XX_PLL_SECCTL_RG_ADDR)
156 #define C66XX_set_pll_secctl_rg(v)							C66XX_SET_RG_VALUE(C66XX_PLL_SECCTL_RG_ADDR, v)
157 
158 	// dedicated bit specific macros
159 #define C66XX_get_pll_secctl_bypass()						C66XX_GET_FIELD_VALUE(C66XX_PLL_SECCTL_RG_ADDR, PLL_SECCTL_BYPASS)
160 #define C66XX_set_pll_secctl_bypass(v)						C66XX_SET_FIELD_VALUE(C66XX_PLL_SECCTL_RG_ADDR, PLL_SECCTL_BYPASS, v)
161 #define C66XX_get_pll_secctl_output_divide()				C66XX_GET_FIELD_VALUE(C66XX_PLL_SECCTL_RG_ADDR, PLL_SECCTL_OUTPUT_DIVIDE)
162 #define C66XX_set_pll_secctl_output_divide(v)				C66XX_SET_FIELD_VALUE(C66XX_PLL_SECCTL_RG_ADDR, PLL_SECCTL_OUTPUT_DIVIDE, v)
163 
164 	// direct bit set macros
165 #define C66XX_SET_PLL_SECCTL_BYPASS_ON						C66XX_set_pll_secctl_bypass(C66XX_ON)
166 #define C66XX_SET_PLL_SECCTL_BYPASS_OFF						C66XX_set_pll_secctl_bypass(C66XX_OFF)
167 
168 	// condition check macros (for use in IF() and other conditional operators)
169 #define C66XX_PLL_SECCTL_BYPASS_IS_ON						(C66XX_get_pll_secctl_bypass() == C66XX_ON)
170 
171 
172 //------------ PLL multiplier control register macros -------------------------
173 #define C66XX_get_pll_pllm_rg()								C66XX_GET_RG_VALUE(C66XX_PLL_PLLM_RG_ADDR)
174 #define C66XX_set_pll_pllm_rg(v)							C66XX_SET_RG_VALUE(C66XX_PLL_PLLM_RG_ADDR, v)
175 
176 	// dedicated bit specific macros
177 #define C66XX_get_pll_pllm_pllm()							C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLM_RG_ADDR, PLL_PLLM_PLLM)
178 #define C66XX_set_pll_pllm_pllm(v)							C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLM_RG_ADDR, PLL_PLLM_PLLM, v)
179 
180 
181 //------------ PLL controller divider registers macros ------------------------
182 // i index corresonds to PLL controller divider registers number
183 // Note that i index should be from 0 to 15 instead of 1 to 16 !!!
184 #define C66XX_get_pll_plldiv_rg_addr(i)						(i < 3 ? (C66XX_PLL_PLLDIV1_RG_ADDR + i * 0x4) : (C66XX_PLL_PLLDIV4_RG_ADDR + (i - 3) * 0x4))
185 #define C66XX_get_pll_plldiv_rg(i)							C66XX_GET_RG_VALUE(C66XX_get_pll_plldiv_rg_addr(i))
186 #define C66XX_set_pll_plldiv_rg(i, v)						C66XX_SET_RG_VALUE(C66XX_get_pll_plldiv_rg_addr(i), v)
187 
188 	// dedicated bit specific macros
189 #define C66XX_get_pll_plldiv_den(i)							C66XX_GET_FIELD_VALUE(C66XX_get_pll_plldiv_rg_addr(i), PLL_PLLDIV_DEN)
190 #define C66XX_set_pll_plldiv_den(i, v)						C66XX_SET_FIELD_VALUE(C66XX_get_pll_plldiv_rg_addr(i), PLL_PLLDIV_DEN, v)
191 #define C66XX_get_pll_plldiv_ratio(i)						C66XX_GET_FIELD_VALUE(C66XX_get_pll_plldiv_rg_addr(i), PLL_PLLDIV_RATIO)
192 #define C66XX_set_pll_plldiv_ratio(i, v)					C66XX_SET_FIELD_VALUE(C66XX_get_pll_plldiv_rg_addr(i), PLL_PLLDIV_RATIO, v)
193 
194 	// direct bit set macros
195 #define C66XX_SET_PLL_PLLDIV_DEN_ON(i)						C66XX_set_pll_plldiv_den(i, C66XX_ON)
196 #define C66XX_SET_PLL_PLLDIV_DEN_OFF(i)						C66XX_set_pll_plldiv_den(i, C66XX_OFF)
197 
198 	// condition check macros (for use in IF() and other conditional operators)
199 #define C66XX_PLL_PLLDIV_DEN_IS_ON(i)						(C66XX_get_pll_plldiv_den(i) == C66XX_ON)
200 
201 
202 //------------ PLL controller command register macros -------------------------
203 #define C66XX_get_pll_pllcmd_rg()							C66XX_GET_RG_VALUE(C66XX_PLL_PLLCMD_RG_ADDR)
204 #define C66XX_set_pll_pllcmd_rg(v)							C66XX_SET_RG_VALUE(C66XX_PLL_PLLCMD_RG_ADDR, v)
205 
206 	// dedicated bit specific macros
207 #define C66XX_get_pll_pllcmd_goset()						C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLCMD_RG_ADDR, PLL_PLLCMD_GOSET)
208 #define C66XX_set_pll_pllcmd_goset(v)						C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCMD_RG_ADDR, PLL_PLLCMD_GOSET, v)
209 
210 	// direct bit set macros
211 #define C66XX_SET_PLL_PLLCMD_GOSET_ON						C66XX_set_pll_pllcmd_goset(C66XX_ON)
212 #define C66XX_SET_PLL_PLLCMD_GOSET_OFF						C66XX_set_pll_pllcmd_goset(C66XX_OFF)
213 
214 	// condition check macros (for use in IF() and other conditional operators)
215 #define C66XX_PLL_PLLCMD_GOSET_IS_ON						(C66XX_get_pll_pllcmd_goset() == C66XX_ON)
216 
217 
218 //------------ PLL controller status register macros --------------------------
219 #define C66XX_get_pll_pllstat_rg()							C66XX_GET_RG_VALUE(C66XX_PLL_PLLSTAT_RG_ADDR)
220 #define C66XX_set_pll_pllstat_rg(v)							C66XX_SET_RG_VALUE(C66XX_PLL_PLLSTAT_RG_ADDR, v)
221 
222 	// dedicated bit specific macros
223 #define C66XX_get_pll_pllstat_gostat()						C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLSTAT_RG_ADDR, PLL_PLLSTAT_GOSTAT)
224 #define C66XX_set_pll_pllstat_gostat(v)						C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLSTAT_RG_ADDR, PLL_PLLSTAT_GOSTAT, v)
225 
226 	// direct bit set macros
227 #define C66XX_SET_PLL_PLLSTAT_GOSTAT_ON						C66XX_set_pll_pllstat_gostat(C66XX_ON)
228 #define C66XX_SET_PLL_PLLSTAT_GOSTAT_OFF					C66XX_set_pll_pllstat_gostat(C66XX_OFF)
229 
230 	// condition check macros (for use in IF() and other conditional operators)
231 #define C66XX_PLL_PLLSTAT_GOSTAT_IS_ON						(C66XX_get_pll_pllstat_gostat() == C66XX_ON)
232 
233 
234 //------------ PLL controller clock align control register macros -------------
235 #define C66XX_get_pll_alnctl_rg()							C66XX_GET_RG_VALUE(C66XX_PLL_ALNCTL_RG_ADDR)
236 #define C66XX_set_pll_alnctl_rg(v)							C66XX_SET_RG_VALUE(C66XX_PLL_ALNCTL_RG_ADDR, v)
237 
238 	// dedicated bit specific macros
239 #define C66XX_get_pll_alnctl_aln()							C66XX_GET_FIELD_VALUE(C66XX_PLL_ALNCTL_RG_ADDR, PLL_ALNCTL_ALN)
240 #define C66XX_set_pll_alnctl_aln(v)							C66XX_SET_FIELD_VALUE(C66XX_PLL_ALNCTL_RG_ADDR, PLL_ALNCTL_ALN, v)
241 
242 
243 //------------ PLL controller divider ratio change status register macros -----
244 #define C66XX_get_pll_dchange_rg()							C66XX_GET_RG_VALUE(C66XX_PLL_DCHANGE_RG_ADDR)
245 #define C66XX_set_pll_dchange_rg(v)							C66XX_SET_RG_VALUE(C66XX_PLL_DCHANGE_RG_ADDR, v)
246 
247 	// dedicated bit specific macros
248 #define C66XX_get_pll_dchange_sys()							C66XX_GET_FIELD_VALUE(C66XX_PLL_DCHANGE_RG_ADDR, PLL_DCHANGE_SYS)
249 #define C66XX_set_pll_dchange_sys(v)						C66XX_SET_FIELD_VALUE(C66XX_PLL_DCHANGE_RG_ADDR, PLL_DCHANGE_SYS, v)
250 
251 
252 //------------ SYSCLK status register macros ----------------------------------
253 #define C66XX_get_pll_systat_rg()							C66XX_GET_RG_VALUE(C66XX_PLL_SYSTAT_RG_ADDR)
254 
255 	// dedicated bit specific macros
256 #define C66XX_get_pll_systat_syson()						C66XX_GET_FIELD_VALUE(C66XX_PLL_SYSTAT_RG_ADDR, PLL_SYSTAT_SYSON)
257 
258 //=============================================================================
259 
260 
261 
262 //=============================================================================
263 //============ Device State Control registers macros ==========================
264 //=============================================================================
265 
266 //------------ Main PLL Control register 0 macros -----------------------------
267 #define C66XX_get_bootcfg_mainpllctl0_rg()					C66XX_GET_RG_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR)
268 #define C66XX_set_bootcfg_mainpllctl0_rg(v)					C66XX_SET_RG_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, v)
269 
270 	// dedicated bit specific macros
271 #define C66XX_get_bootcfg_mainpllctl0_bwadj()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_BWADJ)
272 #define C66XX_set_bootcfg_mainpllctl0_bwadj(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_BWADJ, v)
273 #define C66XX_get_bootcfg_mainpllctl0_pllm()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_PLLM)
274 #define C66XX_set_bootcfg_mainpllctl0_pllm(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_PLLM, v)
275 #define C66XX_get_bootcfg_mainpllctl0_plld()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_PLLD)
276 #define C66XX_set_bootcfg_mainpllctl0_plld(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_PLLD, v)
277 
278 
279 //------------ Main PLL Control register 1 macros -----------------------------
280 #define C66XX_get_bootcfg_mainpllctl1_rg()					C66XX_GET_RG_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR)
281 #define C66XX_set_bootcfg_mainpllctl1_rg(v)					C66XX_SET_RG_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR, v)
282 
283 	// dedicated bit specific macros
284 #define C66XX_get_bootcfg_mainpllctl1_ensat()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR, BOOTCFG_MAINPLLCTL1_ENSAT)
285 #define C66XX_set_bootcfg_mainpllctl1_ensat(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR, BOOTCFG_MAINPLLCTL1_ENSAT, v)
286 #define C66XX_get_bootcfg_mainpllctl1_bwadj()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR, BOOTCFG_MAINPLLCTL1_BWADJ)
287 #define C66XX_set_bootcfg_mainpllctl1_bwadj(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR, BOOTCFG_MAINPLLCTL1_BWADJ, v)
288 
289 	// direct bit set macros
290 #define C66XX_SET_BOOTCFG_MAINPLLCTL1_ENSAT_ON				C66XX_set_bootcfg_mainpllctl1_ensat(C66XX_ON)
291 #define C66XX_SET_BOOTCFG_MAINPLLCTL1_ENSAT_OFF				C66XX_set_bootcfg_mainpllctl1_ensat(C66XX_OFF)
292 
293 	// condition check macros (for use in IF() and other conditional operators)
294 #define C66XX_BOOTCFG_MAINPLLCTL1_ENSAT_IS_ON				(C66XX_get_bootcfg_mainpllctl1_ensat() == C66XX_ON)
295 
296 
297 //------------ DDR3 PLL Control register 0 macros -----------------------------
298 #define C66XX_get_bootcfg_ddr3pllctl0_rg()					C66XX_GET_RG_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR)
299 #define C66XX_set_bootcfg_ddr3pllctl0_rg(v)					C66XX_SET_RG_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, v)
300 
301 	// dedicated bit specific macros
302 #define C66XX_get_bootcfg_ddr3pllctl0_bwadj()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_BWADJ)
303 #define C66XX_set_bootcfg_ddr3pllctl0_bwadj(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_BWADJ, v)
304 #define C66XX_get_bootcfg_ddr3pllctl0_bypass()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_BYPASS)
305 #define C66XX_set_bootcfg_ddr3pllctl0_bypass(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_BYPASS, v)
306 #define C66XX_get_bootcfg_ddr3pllctl0_pllm()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_PLLM)
307 #define C66XX_set_bootcfg_ddr3pllctl0_pllm(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_PLLM, v)
308 #define C66XX_get_bootcfg_ddr3pllctl0_plld()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_PLLD)
309 #define C66XX_set_bootcfg_ddr3pllctl0_plld(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_PLLD, v)
310 
311 	// direct bit set macros
312 #define C66XX_SET_BOOTCFG_DDR3PLLCTL0_BYPASS_ON				C66XX_set_bootcfg_ddr3pllctl0_bypass(C66XX_ON)
313 #define C66XX_SET_BOOTCFG_DDR3PLLCTL0_BYPASS_OFF			C66XX_set_bootcfg_ddr3pllctl0_bypass(C66XX_OFF)
314 
315 	// condition check macros (for use in IF() and other conditional operators)
316 #define C66XX_BOOTCFG_DDR3PLLCTL0_BYPASS_IS_ON				(C66XX_get_bootcfg_ddr3pllctl0_bypass() == C66XX_ON)
317 
318 
319 //------------ DDR3 PLL Control register 1 macros -----------------------------
320 #define C66XX_get_bootcfg_ddr3pllctl1_rg()					C66XX_GET_RG_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR)
321 #define C66XX_set_bootcfg_ddr3pllctl1_rg(v)					C66XX_SET_RG_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, v)
322 
323 	// dedicated bit specific macros
324 #define C66XX_get_bootcfg_ddr3pllctl1_pllrst()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_PLLRST)
325 #define C66XX_set_bootcfg_ddr3pllctl1_pllrst(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_PLLRST, v)
326 #define C66XX_get_bootcfg_ddr3pllctl1_ensat()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_ENSAT)
327 #define C66XX_set_bootcfg_ddr3pllctl1_ensat(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_ENSAT, v)
328 #define C66XX_get_bootcfg_ddr3pllctl1_bwadj()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_BWADJ)
329 #define C66XX_set_bootcfg_ddr3pllctl1_bwadj(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_BWADJ, v)
330 
331 	// direct bit set macros
332 #define C66XX_SET_BOOTCFG_DDR3PLLCTL1_PLLRST_ON				C66XX_set_bootcfg_ddr3pllctl1_pllrst(C66XX_ON)
333 #define C66XX_SET_BOOTCFG_DDR3PLLCTL1_PLLRST_OFF			C66XX_set_bootcfg_ddr3pllctl1_pllrst(C66XX_OFF)
334 #define C66XX_SET_BOOTCFG_DDR3PLLCTL1_ENSAT_ON				C66XX_set_bootcfg_ddr3pllctl1_ensat(C66XX_ON)
335 #define C66XX_SET_BOOTCFG_DDR3PLLCTL1_ENSAT_OFF				C66XX_set_bootcfg_ddr3pllctl1_ensat(C66XX_OFF)
336 
337 	// condition check macros (for use in IF() and other conditional operators)
338 #define C66XX_BOOTCFG_DDR3PLLCTL1_PLLRST_IS_ON				(C66XX_get_bootcfg_ddr3pllctl1_pllrst() == C66XX_ON)
339 #define C66XX_BOOTCFG_DDR3PLLCTL1_ENSAT_IS_ON				(C66XX_get_bootcfg_ddr3pllctl1_ensat() == C66XX_ON)
340 
341 
342 //------------ PASS PLL Control register 0 macros -----------------------------
343 #define C66XX_get_bootcfg_passpllctl0_rg()					C66XX_GET_RG_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR)
344 #define C66XX_set_bootcfg_passpllctl0_rg(v)					C66XX_SET_RG_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, v)
345 
346 	// dedicated bit specific macros
347 #define C66XX_get_bootcfg_passpllctl0_bwadj()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_BWADJ)
348 #define C66XX_set_bootcfg_passpllctl0_bwadj(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_BWADJ, v)
349 #define C66XX_get_bootcfg_passpllctl0_bypass()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_BYPASS)
350 #define C66XX_set_bootcfg_passpllctl0_bypass(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_BYPASS, v)
351 #define C66XX_get_bootcfg_passpllctl0_pllm()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_PLLM)
352 #define C66XX_set_bootcfg_passpllctl0_pllm(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_PLLM, v)
353 #define C66XX_get_bootcfg_passpllctl0_plld()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_PLLD)
354 #define C66XX_set_bootcfg_passpllctl0_plld(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_PLLD, v)
355 
356 	// direct bit set macros
357 #define C66XX_SET_BOOTCFG_PASSPLLCTL0_BYPASS_ON				C66XX_set_bootcfg_passpllctl0_bypass(C66XX_ON)
358 #define C66XX_SET_BOOTCFG_PASSPLLCTL0_BYPASS_OFF			C66XX_set_bootcfg_passpllctl0_bypass(C66XX_OFF)
359 
360 	// condition check macros (for use in IF() and other conditional operators)
361 #define C66XX_BOOTCFG_PASSPLLCTL0_BYPASS_IS_ON				(C66XX_get_bootcfg_passpllctl0_bypass() == C66XX_ON)
362 
363 
364 //------------ PASS PLL Control register 1 macros -----------------------------
365 #define C66XX_get_bootcfg_passpllctl1_rg()					C66XX_GET_RG_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR)
366 #define C66XX_set_bootcfg_passpllctl1_rg(v)					C66XX_SET_RG_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, v)
367 
368 	// dedicated bit specific macros
369 #define C66XX_get_bootcfg_passpllctl1_pllrst()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_PLLRST)
370 #define C66XX_set_bootcfg_passpllctl1_pllrst(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_PLLRST, v)
371 #define C66XX_get_bootcfg_passpllctl1_pllselect()			C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_PLLSELECT)
372 #define C66XX_set_bootcfg_passpllctl1_pllselect(v)			C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_PLLSELECT, v)
373 #define C66XX_get_bootcfg_passpllctl1_ensat()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_ENSAT)
374 #define C66XX_set_bootcfg_passpllctl1_ensat(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_ENSAT, v)
375 #define C66XX_get_bootcfg_passpllctl1_bwadj()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_BWADJ)
376 #define C66XX_set_bootcfg_passpllctl1_bwadj(v)				C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_BWADJ, v)
377 
378 	// direct bit set macros
379 #define C66XX_SET_BOOTCFG_PASSPLLCTL1_PLLRST_ON				C66XX_set_bootcfg_passpllctl1_pllrst(C66XX_ON)
380 #define C66XX_SET_BOOTCFG_PASSPLLCTL1_PLLRST_OFF			C66XX_set_bootcfg_passpllctl1_pllrst(C66XX_OFF)
381 #define C66XX_SET_BOOTCFG_PASSPLLCTL1_PLLSELECT_ON			C66XX_set_bootcfg_passpllctl1_pllselect(C66XX_ON)
382 #define C66XX_SET_BOOTCFG_PASSPLLCTL1_PLLSELECT_OFF			C66XX_set_bootcfg_passpllctl1_pllselect(C66XX_OFF)
383 #define C66XX_SET_BOOTCFG_PASSPLLCTL1_ENSAT_ON				C66XX_set_bootcfg_passpllctl1_ensat(C66XX_ON)
384 #define C66XX_SET_BOOTCFG_PASSPLLCTL1_ENSAT_OFF				C66XX_set_bootcfg_passpllctl1_ensat(C66XX_OFF)
385 
386 	// condition check macros (for use in IF() and other conditional operators)
387 #define C66XX_BOOTCFG_PASSPLLCTL1_PLLRST_IS_ON				(C66XX_get_bootcfg_passpllctl1_pllrst() == C66XX_ON)
388 #define C66XX_BOOTCFG_PASSPLLCTL1_PLLSELECT_IS_ON			(C66XX_get_bootcfg_passpllctl1_pllselect() == C66XX_ON)
389 #define C66XX_BOOTCFG_PASSPLLCTL1_ENSAT_IS_ON				(C66XX_get_bootcfg_passpllctl1_ensat() == C66XX_ON)
390 
391 
392 //------------ Device speed register macros -----------------------------------
393 #define C66XX_get_bootcfg_devspeed_rg()						C66XX_GET_RG_VALUE(C66XX_BOOTCFG_DEVSPEED_RG_ADDR)
394 	// dedicated bit specific macros
395 #define C66XX_get_bootcfg_devspeed_devspeed()				C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DEVSPEED_RG_ADDR, BOOTCFG_DEVSPEED_DEVSPEED)
396 
397 //=============================================================================
398 
399 
400 
401 //=============================================================================
402 //============ I2C registers macros ===========================================
403 //=============================================================================
404 
405 //------------ I2C own address register macros --------------------------------
406 #define C66XX_get_i2c_icoar_rg()							C66XX_GET_RG_VALUE(C66XX_I2C_ICOAR_RG_ADDR)
407 #define C66XX_set_i2c_icoar_rg(v)							C66XX_SET_RG_VALUE(C66XX_I2C_ICOAR_RG_ADDR, v)
408 
409 	// dedicated bit specific macros
410 #define C66XX_get_i2c_icoar_oaddr()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICOAR_RG_ADDR, I2C_ICOAR_OADDR)
411 #define C66XX_set_i2c_icoar_oaddr(v)						C66XX_SET_FIELD_VALUE(C66XX_I2C_ICOAR_RG_ADDR, I2C_ICOAR_OADDR, v)
412 
413 
414 //------------ I2C interrupt mask register macros -----------------------------
415 #define C66XX_get_i2c_icimr_rg()							C66XX_GET_RG_VALUE(C66XX_I2C_ICIMR_RG_ADDR)
416 #define C66XX_set_i2c_icimr_rg(v)							C66XX_SET_RG_VALUE(C66XX_I2C_ICIMR_RG_ADDR, v)
417 
418 	// dedicated bit specific macros
419 #define C66XX_get_i2c_icimr_aas()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_AAS)
420 #define C66XX_set_i2c_icimr_aas(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_AAS, v)
421 #define C66XX_get_i2c_icimr_scd()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_SCD)
422 #define C66XX_set_i2c_icimr_scd(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_SCD, v)
423 #define C66XX_get_i2c_icimr_icxrdy()						C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ICXRDY)
424 #define C66XX_set_i2c_icimr_icxrdy(v)						C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ICXRDY, v)
425 #define C66XX_get_i2c_icimr_icrdrdy()						C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ICRDRDY)
426 #define C66XX_set_i2c_icimr_icrdrdy(v)						C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ICRDRDY, v)
427 #define C66XX_get_i2c_icimr_ardy()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ARDY)
428 #define C66XX_set_i2c_icimr_ardy(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ARDY, v)
429 #define C66XX_get_i2c_icimr_nack()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_NACK)
430 #define C66XX_set_i2c_icimr_nack(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_NACK, v)
431 #define C66XX_get_i2c_icimr_al()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_AL)
432 #define C66XX_set_i2c_icimr_al(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_AL, v)
433 
434 	// direct bit set macros
435 #define C66XX_SET_I2C_ICIMR_AAS_ON							C66XX_set_i2c_icimr_aas(C66XX_ON)
436 #define C66XX_SET_I2C_ICIMR_AAS_OFF							C66XX_set_i2c_icimr_aas(C66XX_OFF)
437 #define C66XX_SET_I2C_ICIMR_SCD_ON							C66XX_set_i2c_icimr_scd(C66XX_ON)
438 #define C66XX_SET_I2C_ICIMR_SCD_OFF							C66XX_set_i2c_icimr_scd(C66XX_OFF)
439 #define C66XX_SET_I2C_ICIMR_ICXRDY_ON						C66XX_set_i2c_icimr_icxrdy(C66XX_ON)
440 #define C66XX_SET_I2C_ICIMR_ICXRDY_OFF						C66XX_set_i2c_icimr_icxrdy(C66XX_OFF)
441 #define C66XX_SET_I2C_ICIMR_ICRDRDY_ON						C66XX_set_i2c_icimr_icrdrdy(C66XX_ON)
442 #define C66XX_SET_I2C_ICIMR_ICRDRDY_OFF						C66XX_set_i2c_icimr_icrdrdy(C66XX_OFF)
443 #define C66XX_SET_I2C_ICIMR_ARDY_ON							C66XX_set_i2c_icimr_ardy(C66XX_ON)
444 #define C66XX_SET_I2C_ICIMR_ARDY_OFF						C66XX_set_i2c_icimr_ardy(C66XX_OFF)
445 #define C66XX_SET_I2C_ICIMR_NACK_ON							C66XX_set_i2c_icimr_nack(C66XX_ON)
446 #define C66XX_SET_I2C_ICIMR_NACK_OFF						C66XX_set_i2c_icimr_nack(C66XX_OFF)
447 #define C66XX_SET_I2C_ICIMR_AL_ON							C66XX_set_i2c_icimr_al(C66XX_ON)
448 #define C66XX_SET_I2C_ICIMR_AL_OFF							C66XX_set_i2c_icimr_al(C66XX_OFF)
449 
450 	// condition check macros (for use in IF() and other conditional operators)
451 #define C66XX_I2C_ICIMR_AAS_IS_ON							(C66XX_get_i2c_icimr_aas() == C66XX_ON)
452 #define C66XX_I2C_ICIMR_SCD_IS_ON							(C66XX_get_i2c_icimr_scd() == C66XX_ON)
453 #define C66XX_I2C_ICIMR_ICXRDY_IS_ON						(C66XX_get_i2c_icimr_icxrdy() == C66XX_ON)
454 #define C66XX_I2C_ICIMR_ICRDRDY_IS_ON						(C66XX_get_i2c_icimr_icrdrdy() == C66XX_ON)
455 #define C66XX_I2C_ICIMR_ARDY_IS_ON							(C66XX_get_i2c_icimr_ardy() == C66XX_ON)
456 #define C66XX_I2C_ICIMR_NACK_IS_ON							(C66XX_get_i2c_icimr_nack() == C66XX_ON)
457 #define C66XX_I2C_ICIMR_AL_IS_ON							(C66XX_get_i2c_icimr_al() == C66XX_ON)
458 
459 
460 //------------ I2C interrupt status register macros ---------------------------
461 #define C66XX_get_i2c_icstr_rg()							C66XX_GET_RG_VALUE(C66XX_I2C_ICSTR_RG_ADDR)
462 #define C66XX_set_i2c_icstr_rg(v)							C66XX_SET_RG_VALUE(C66XX_I2C_ICSTR_RG_ADDR, v)
463 
464 	// dedicated bit specific macros
465 #define C66XX_get_i2c_icstr_sdir()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_SDIR)
466 #define C66XX_set_i2c_icstr_sdir(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_SDIR, v)
467 #define C66XX_get_i2c_icstr_nacksnt()						C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_NACKSNT)
468 #define C66XX_set_i2c_icstr_nacksnt(v)						C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_NACKSNT, v)
469 #define C66XX_get_i2c_icstr_bb()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_BB)
470 #define C66XX_set_i2c_icstr_bb(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_BB, v)
471 #define C66XX_get_i2c_icstr_rsfull()						C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_RSFULL)
472 #define C66XX_get_i2c_icstr_xsmt()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_XSMT)
473 #define C66XX_get_i2c_icstr_aas()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_AAS)
474 #define C66XX_get_i2c_icstr_ad0()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_AD0)
475 #define C66XX_get_i2c_icstr_scd()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_SCD)
476 #define C66XX_set_i2c_icstr_scd(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_SCD, v)
477 #define C66XX_get_i2c_icstr_icxrdy()						C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ICXRDY)
478 #define C66XX_set_i2c_icstr_icxrdy(v)						C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ICXRDY, v)
479 #define C66XX_get_i2c_icstr_icrdrdy()						C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ICRDRDY)
480 #define C66XX_set_i2c_icstr_icrdrdy(v)						C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ICRDRDY, v)
481 #define C66XX_get_i2c_icstr_ardy()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ARDY)
482 #define C66XX_set_i2c_icstr_ardy(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ARDY, v)
483 #define C66XX_get_i2c_icstr_nack()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_NACK)
484 #define C66XX_set_i2c_icstr_nack(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_NACK, v)
485 #define C66XX_get_i2c_icstr_al()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_AL)
486 #define C66XX_set_i2c_icstr_al(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_AL, v)
487 
488 	// direct bit set macros
489 #define C66XX_CLEAR_I2C_ICSTR_SDIR							C66XX_set_i2c_icstr_sdir(C66XX_ON)
490 #define C66XX_CLEAR_I2C_ICSTR_NACKSNT						C66XX_set_i2c_icstr_nacksnt(C66XX_ON)
491 #define C66XX_CLEAR_I2C_ICSTR_BB							C66XX_set_i2c_icstr_bb(C66XX_ON)
492 #define C66XX_CLEAR_I2C_ICSTR_SCD							C66XX_set_i2c_icstr_scd(C66XX_ON)
493 #define C66XX_CLEAR_I2C_ICSTR_ICXRDY						C66XX_set_i2c_icstr_icxrdy(C66XX_ON)
494 #define C66XX_CLEAR_I2C_ICSTR_ICRDRDY						C66XX_set_i2c_icstr_icrdrdy(C66XX_ON)
495 #define C66XX_CLEAR_I2C_ICSTR_ARDY							C66XX_set_i2c_icstr_ardy(C66XX_ON)
496 #define C66XX_CLEAR_I2C_ICSTR_NACK							C66XX_set_i2c_icstr_nack(C66XX_ON)
497 #define C66XX_CLEAR_I2C_ICSTR_AL							C66XX_set_i2c_icstr_al(C66XX_ON)
498 
499 	// condition check macros (for use in IF() and other conditional operators)
500 #define C66XX_I2C_ICSTR_SDIR_IS_ON							(C66XX_get_i2c_icstr_sdir() == C66XX_ON)
501 #define C66XX_I2C_ICSTR_NACKSNT_IS_ON						(C66XX_get_i2c_icstr_nacksnt() == C66XX_ON)
502 #define C66XX_I2C_ICSTR_BB_IS_ON							(C66XX_get_i2c_icstr_bb() == C66XX_ON)
503 #define C66XX_I2C_ICSTR_RSFULL_IS_ON						(C66XX_get_i2c_icstr_rsfull() == C66XX_ON)
504 #define C66XX_I2C_ICSTR_XSMT_IS_ON							(C66XX_get_i2c_icstr_xsmt() == C66XX_ON)
505 #define C66XX_I2C_ICSTR_AAS_IS_ON							(C66XX_get_i2c_icstr_aas() == C66XX_ON)
506 #define C66XX_I2C_ICSTR_AD0_IS_ON							(C66XX_get_i2c_icstr_ad0() == C66XX_ON)
507 #define C66XX_I2C_ICSTR_SCD_IS_ON							(C66XX_get_i2c_icstr_scd() == C66XX_ON)
508 #define C66XX_I2C_ICSTR_ICXRDY_IS_ON						(C66XX_get_i2c_icstr_icxrdy() == C66XX_ON)
509 #define C66XX_I2C_ICSTR_ICRDRDY_IS_ON						(C66XX_get_i2c_icstr_icrdrdy() == C66XX_ON)
510 #define C66XX_I2C_ICSTR_ARDY_IS_ON							(C66XX_get_i2c_icstr_ardy() == C66XX_ON)
511 #define C66XX_I2C_ICSTR_NACK_IS_ON							(C66XX_get_i2c_icstr_nack() == C66XX_ON)
512 #define C66XX_I2C_ICSTR_AL_IS_ON							(C66XX_get_i2c_icstr_al() == C66XX_ON)
513 
514 
515 //------------ I2C clock low-time divider register macros ---------------------
516 #define C66XX_get_i2c_icclkl_rg()							C66XX_GET_RG_VALUE(C66XX_I2C_ICCLKL_RG_ADDR)
517 #define C66XX_set_i2c_icclkl_rg(v)							C66XX_SET_RG_VALUE(C66XX_I2C_ICCLKL_RG_ADDR, v)
518 
519 	// dedicated bit specific macros
520 #define C66XX_get_i2c_icclkl_iccl()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICCLKL_RG_ADDR, I2C_ICCLKL_ICCL)
521 #define C66XX_set_i2c_icclkl_iccl(v)						C66XX_SET_FIELD_VALUE(C66XX_I2C_ICCLKL_RG_ADDR, I2C_ICCLKL_ICCL, v)
522 
523 
524 //------------ I2C clock high-time divider register macros --------------------
525 #define C66XX_get_i2c_icclkh_rg()							C66XX_GET_RG_VALUE(C66XX_I2C_ICCLKH_RG_ADDR)
526 #define C66XX_set_i2c_icclkh_rg(v)							C66XX_SET_RG_VALUE(C66XX_I2C_ICCLKH_RG_ADDR, v)
527 
528 	// dedicated bit specific macros
529 #define C66XX_get_i2c_icclkh_icch()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICCLKH_RG_ADDR, I2C_ICCLKH_ICCH)
530 #define C66XX_set_i2c_icclkh_icch(v)						C66XX_SET_FIELD_VALUE(C66XX_I2C_ICCLKH_RG_ADDR, I2C_ICCLKH_ICCH, v)
531 
532 
533 //------------ I2C data count register macros ---------------------------------
534 #define C66XX_get_i2c_iccnt_rg()							C66XX_GET_RG_VALUE(C66XX_I2C_ICCNT_RG_ADDR)
535 #define C66XX_set_i2c_iccnt_rg(v)							C66XX_SET_RG_VALUE(C66XX_I2C_ICCNT_RG_ADDR, v)
536 
537 	// dedicated bit specific macros
538 #define C66XX_get_i2c_iccnt_icdc()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICCNT_RG_ADDR, I2C_ICCNT_ICDC)
539 #define C66XX_set_i2c_iccnt_icdc(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICCNT_RG_ADDR, I2C_ICCNT_ICDC, v)
540 
541 
542 //------------ I2C data receive register macros -------------------------------
543 #define C66XX_get_i2c_icdrr_rg()							C66XX_GET_RG_VALUE(C66XX_I2C_ICDRR_RG_ADDR)
544 
545 	// dedicated bit specific macros
546 #define C66XX_get_i2c_icdrr_d()								C66XX_GET_FIELD_VALUE(C66XX_I2C_ICDRR_RG_ADDR, I2C_ICDRR_D)
547 
548 
549 //------------ I2C slave address register macros ------------------------------
550 #define C66XX_get_i2c_icsar_rg()							C66XX_GET_RG_VALUE(C66XX_I2C_ICSAR_RG_ADDR)
551 #define C66XX_set_i2c_icsar_rg(v)							C66XX_SET_RG_VALUE(C66XX_I2C_ICSAR_RG_ADDR, v)
552 
553 	// dedicated bit specific macros
554 #define C66XX_get_i2c_icsar_saddr()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSAR_RG_ADDR, I2C_ICSAR_SADDR)
555 #define C66XX_set_i2c_icsar_saddr(v)						C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSAR_RG_ADDR, I2C_ICSAR_SADDR, v)
556 
557 
558 //------------ I2C data transmit register macros ------------------------------
559 #define C66XX_get_i2c_icdxr_rg()							C66XX_GET_RG_VALUE(C66XX_I2C_ICDXR_RG_ADDR)
560 #define C66XX_set_i2c_icdxr_rg(v)							C66XX_SET_RG_VALUE(C66XX_I2C_ICDXR_RG_ADDR, v)
561 
562 	// dedicated bit specific macros
563 #define C66XX_get_i2c_icdxr_d()								C66XX_GET_FIELD_VALUE(C66XX_I2C_ICDXR_RG_ADDR, I2C_ICDXR_D)
564 #define C66XX_set_i2c_icdxr_d(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICDXR_RG_ADDR, I2C_ICDXR_D, v)
565 
566 
567 //------------ I2C mode register macros ---------------------------------------
568 #define C66XX_get_i2c_icmdr_rg()							C66XX_GET_RG_VALUE(C66XX_I2C_ICMDR_RG_ADDR)
569 #define C66XX_set_i2c_icmdr_rg(v)							C66XX_SET_RG_VALUE(C66XX_I2C_ICMDR_RG_ADDR, v)
570 
571 	// dedicated bit specific macros
572 #define C66XX_get_i2c_icmdr_nackmod()						C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_NACKMOD)
573 #define C66XX_set_i2c_icmdr_nackmod(v)						C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_NACKMOD, v)
574 #define C66XX_get_i2c_icmdr_free()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_FREE)
575 #define C66XX_set_i2c_icmdr_free(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_FREE, v)
576 #define C66XX_get_i2c_icmdr_stt()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STT)
577 #define C66XX_set_i2c_icmdr_stt(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STT, v)
578 #define C66XX_get_i2c_icmdr_stp()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STP)
579 #define C66XX_set_i2c_icmdr_stp(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STP, v)
580 #define C66XX_get_i2c_icmdr_mst()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_MST)
581 #define C66XX_set_i2c_icmdr_mst(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_MST, v)
582 #define C66XX_get_i2c_icmdr_trx()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_TRX)
583 #define C66XX_set_i2c_icmdr_trx(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_TRX, v)
584 #define C66XX_get_i2c_icmdr_xa()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_XA)
585 #define C66XX_set_i2c_icmdr_xa(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_XA, v)
586 #define C66XX_get_i2c_icmdr_rm()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_RM)
587 #define C66XX_set_i2c_icmdr_rm(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_RM, v)
588 #define C66XX_get_i2c_icmdr_dlb()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_DLB)
589 #define C66XX_set_i2c_icmdr_dlb(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_DLB, v)
590 #define C66XX_get_i2c_icmdr_irs()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_IRS)
591 #define C66XX_set_i2c_icmdr_irs(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_IRS, v)
592 #define C66XX_get_i2c_icmdr_stb()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STB)
593 #define C66XX_set_i2c_icmdr_stb(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STB, v)
594 #define C66XX_get_i2c_icmdr_fdf()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_FDF)
595 #define C66XX_set_i2c_icmdr_fdf(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_FDF, v)
596 #define C66XX_get_i2c_icmdr_bc()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_BC)
597 #define C66XX_set_i2c_icmdr_bc(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_BC, v)
598 
599 	// direct bit set macros
600 #define C66XX_SET_I2C_ICMDR_NACKMOD_ON						C66XX_set_i2c_icmdr_nackmod(C66XX_ON)
601 #define C66XX_SET_I2C_ICMDR_NACKMOD_OFF						C66XX_set_i2c_icmdr_nackmod(C66XX_OFF)
602 #define C66XX_SET_I2C_ICMDR_FREE_ON							C66XX_set_i2c_icmdr_free(C66XX_ON)
603 #define C66XX_SET_I2C_ICMDR_FREE_OFF						C66XX_set_i2c_icmdr_free(C66XX_OFF)
604 #define C66XX_SET_I2C_ICMDR_STT_ON							C66XX_set_i2c_icmdr_stt(C66XX_ON)
605 #define C66XX_SET_I2C_ICMDR_STT_OFF							C66XX_set_i2c_icmdr_stt(C66XX_OFF)
606 #define C66XX_SET_I2C_ICMDR_STP_ON							C66XX_set_i2c_icmdr_stp(C66XX_ON)
607 #define C66XX_SET_I2C_ICMDR_STP_OFF							C66XX_set_i2c_icmdr_stp(C66XX_OFF)
608 #define C66XX_SET_I2C_ICMDR_MST_ON							C66XX_set_i2c_icmdr_mst(C66XX_ON)
609 #define C66XX_SET_I2C_ICMDR_MST_OFF							C66XX_set_i2c_icmdr_mst(C66XX_OFF)
610 #define C66XX_SET_I2C_ICMDR_TRX_ON							C66XX_set_i2c_icmdr_trx(C66XX_ON)
611 #define C66XX_SET_I2C_ICMDR_TRX_OFF							C66XX_set_i2c_icmdr_trx(C66XX_OFF)
612 #define C66XX_SET_I2C_ICMDR_XA_OFF							C66XX_set_i2c_icmdr_xa(C66XX_OFF)
613 #define C66XX_SET_I2C_ICMDR_XA_ON							C66XX_set_i2c_icmdr_xa(C66XX_ON)
614 #define C66XX_SET_I2C_ICMDR_RM_OFF							C66XX_set_i2c_icmdr_rm(C66XX_OFF)
615 #define C66XX_SET_I2C_ICMDR_RM_ON							C66XX_set_i2c_icmdr_rm(C66XX_ON)
616 #define C66XX_SET_I2C_ICMDR_DLB_OFF							C66XX_set_i2c_icmdr_dlb(C66XX_OFF)
617 #define C66XX_SET_I2C_ICMDR_DLB_ON							C66XX_set_i2c_icmdr_dlb(C66XX_ON)
618 #define C66XX_SET_I2C_ICMDR_IRS_OFF							C66XX_set_i2c_icmdr_irs(C66XX_OFF)
619 #define C66XX_SET_I2C_ICMDR_IRS_ON							C66XX_set_i2c_icmdr_irs(C66XX_ON)
620 #define C66XX_SET_I2C_ICMDR_STB_OFF							C66XX_set_i2c_icmdr_stb(C66XX_OFF)
621 #define C66XX_SET_I2C_ICMDR_STB_ON							C66XX_set_i2c_icmdr_stb(C66XX_ON)
622 #define C66XX_SET_I2C_ICMDR_FDF_OFF							C66XX_set_i2c_icmdr_fdf(C66XX_OFF)
623 #define C66XX_SET_I2C_ICMDR_FDF_ON							C66XX_set_i2c_icmdr_fdf(C66XX_ON)
624 
625 	// condition check macros (for use in IF() and other conditional operators)
626 #define C66XX_I2C_ICMDR_NACKMOD_IS_ON						(C66XX_get_i2c_icmdr_nackmod() == C66XX_ON)
627 #define C66XX_I2C_ICMDR_FREE_IS_ON							(C66XX_get_i2c_icmdr_free() == C66XX_ON)
628 #define C66XX_I2C_ICMDR_STT_IS_ON							(C66XX_get_i2c_icmdr_stt() == C66XX_ON)
629 #define C66XX_I2C_ICMDR_STP_IS_ON							(C66XX_get_i2c_icmdr_stp() == C66XX_ON)
630 #define C66XX_I2C_ICMDR_MST_IS_ON							(C66XX_get_i2c_icmdr_mst() == C66XX_ON)
631 #define C66XX_I2C_ICMDR_TRX_IS_ON							(C66XX_get_i2c_icmdr_trx() == C66XX_ON)
632 #define C66XX_I2C_ICMDR_XA_IS_ON							(C66XX_get_i2c_icmdr_xa() == C66XX_ON)
633 #define C66XX_I2C_ICMDR_RM_IS_ON							(C66XX_get_i2c_icmdr_rm() == C66XX_ON)
634 #define C66XX_I2C_ICMDR_DLB_IS_ON							(C66XX_get_i2c_icmdr_dlb() == C66XX_ON)
635 #define C66XX_I2C_ICMDR_IRS_IS_ON							(C66XX_get_i2c_icmdr_irs() == C66XX_ON)
636 #define C66XX_I2C_ICMDR_STB_IS_ON							(C66XX_get_i2c_icmdr_stb() == C66XX_ON)
637 #define C66XX_I2C_ICMDR_FDF_IS_ON							(C66XX_get_i2c_icmdr_fdf() == C66XX_ON)
638 
639 
640 //------------ I2C interrupt vector register macros ---------------------------
641 #define C66XX_get_i2c_icivr_rg()							C66XX_GET_RG_VALUE(C66XX_I2C_ICIVR_RG_ADDR)
642 
643 	// dedicated bit specific macros
644 #define C66XX_get_i2c_icivr_intcode()						C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIVR_RG_ADDR, I2C_ICIVR_INTCODE)
645 
646 
647 //------------ I2C extended mode register macros ------------------------------
648 #define C66XX_get_i2c_icemdr_rg()							C66XX_GET_RG_VALUE(C66XX_I2C_ICEMDR_RG_ADDR)
649 #define C66XX_set_i2c_icemdr_rg(v)							C66XX_SET_RG_VALUE(C66XX_I2C_ICEMDR_RG_ADDR, v)
650 
651 	// dedicated bit specific macros
652 #define C66XX_get_i2c_icemdr_ignack()						C66XX_GET_FIELD_VALUE(C66XX_I2C_ICEMDR_RG_ADDR, I2C_ICEMDR_IGNACK)
653 #define C66XX_set_i2c_icemdr_ignack(v)						C66XX_SET_FIELD_VALUE(C66XX_I2C_ICEMDR_RG_ADDR, I2C_ICEMDR_IGNACK, v)
654 #define C66XX_get_i2c_icemdr_bcm()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICEMDR_RG_ADDR, I2C_ICEMDR_BCM)
655 #define C66XX_set_i2c_icemdr_bcm(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICEMDR_RG_ADDR, I2C_ICEMDR_BCM, v)
656 
657 	// direct bit set macros
658 #define C66XX_SET_I2C_ICEMDR_IGNACK_ON						C66XX_set_i2c_icemdr_ignack(C66XX_ON)
659 #define C66XX_SET_I2C_ICEMDR_IGNACK_OFF						C66XX_set_i2c_icemdr_ignack(C66XX_OFF)
660 #define C66XX_SET_I2C_ICEMDR_BCM_ON							C66XX_set_i2c_icemdr_bcm(C66XX_ON)
661 #define C66XX_SET_I2C_ICEMDR_BCM_OFF						C66XX_set_i2c_icemdr_bcm(C66XX_OFF)
662 
663 	// condition check macros (for use in IF() and other conditional operators)
664 #define C66XX_I2C_ICEMDR_IGNACK_IS_ON						(C66XX_get_i2c_icemdr_ignack() == C66XX_ON)
665 #define C66XX_I2C_ICEMDR_BCM_IS_ON							(C66XX_get_i2c_icemdr_bcm() == C66XX_ON)
666 
667 
668 //------------ I2C prescaler register macros ----------------------------------
669 #define C66XX_get_i2c_icpsc_rg()							C66XX_GET_RG_VALUE(C66XX_I2C_ICPSC_RG_ADDR)
670 #define C66XX_set_i2c_icpsc_rg(v)							C66XX_SET_RG_VALUE(C66XX_I2C_ICPSC_RG_ADDR, v)
671 
672 	// dedicated bit specific macros
673 #define C66XX_get_i2c_icpsc_ipsc()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICPSC_RG_ADDR, I2C_ICPSC_IPSC)
674 #define C66XX_set_i2c_icpsc_ipsc(v)							C66XX_SET_FIELD_VALUE(C66XX_I2C_ICPSC_RG_ADDR, I2C_ICPSC_IPSC, v)
675 
676 
677 //------------ I2C peripheral identification 1 register macros ----------------
678 #define C66XX_get_i2c_icpid1_rg()							C66XX_GET_RG_VALUE(C66XX_I2C_ICPID1_RG_ADDR)
679 #define C66XX_set_i2c_icpid1_rg(v)							C66XX_SET_RG_VALUE(C66XX_I2C_ICPID1_RG_ADDR, v)
680 
681 	// dedicated bit specific macros
682 #define C66XX_get_i2c_icpid1_class()						C66XX_GET_FIELD_VALUE(C66XX_I2C_ICPID1_RG_ADDR, I2C_ICPID1_CLASS)
683 #define C66XX_set_i2c_icpid1_class(v)						C66XX_SET_FIELD_VALUE(C66XX_I2C_ICPID1_RG_ADDR, I2C_ICPID1_CLASS, v)
684 #define C66XX_get_i2c_icpid1_revision()						C66XX_GET_FIELD_VALUE(C66XX_I2C_ICPID1_RG_ADDR, I2C_ICPID1_REVISION)
685 #define C66XX_set_i2c_icpid1_revision(v)					C66XX_SET_FIELD_VALUE(C66XX_I2C_ICPID1_RG_ADDR, I2C_ICPID1_REVISION, v)
686 
687 
688 //------------ I2C peripheral identification 2 register macros ----------------
689 #define C66XX_get_i2c_icpid2_rg()							C66XX_GET_RG_VALUE(C66XX_I2C_ICPID2_RG_ADDR)
690 #define C66XX_set_i2c_icpid2_rg(v)							C66XX_SET_RG_VALUE(C66XX_I2C_ICPID2_RG_ADDR, v)
691 
692 	// dedicated bit specific macros
693 #define C66XX_get_i2c_icpid2_type()							C66XX_GET_FIELD_VALUE(C66XX_I2C_ICPID2_RG_ADDR, I2C_ICPID2_TYPE)
694 #define C66XX_set_i2c_icpid2_type(v)						C66XX_SET_FIELD_VALUE(C66XX_I2C_ICPID2_RG_ADDR, I2C_ICPID2_TYPE, v)
695 //=============================================================================
696 
697 
698 
699 //=============================================================================
700 //============ EMIF16 configuration macros ====================================
701 //=============================================================================
702 
703 //------------ Revision code and status register macros -----------------------
704 #define C66XX_get_emif16_rcsr_rg()							C66XX_GET_RG_VALUE(C66XX_EMIF16_RCSR_RG_ADDR)
705 
706 	// dedicated bit specific macros
707 #define C66XX_get_emif16_rcsr_be()							C66XX_GET_FIELD_VALUE(C66XX_EMIF16_RCSR_RG_ADDR, EMIF16_RCSR_BE)
708 #define C66XX_get_emif16_rcsr_mod_id()						C66XX_GET_FIELD_VALUE(C66XX_EMIF16_RCSR_RG_ADDR, EMIF16_RCSR_MOD_ID)
709 #define C66XX_get_emif16_rcsr_mj_rev()						C66XX_GET_FIELD_VALUE(C66XX_EMIF16_RCSR_RG_ADDR, EMIF16_RCSR_MJ_REV)
710 #define C66XX_get_emif16_rcsr_min_rev()						C66XX_GET_FIELD_VALUE(C66XX_EMIF16_RCSR_RG_ADDR, EMIF16_RCSR_MIN_REV)
711 
712 	// condition check macros (for use in IF() and other conditional operators)
713 #define C66XX_EMIF16_RCSR_BE_IS_ON							(C66XX_get_emif16_rcsr_be() == C66XX_ON)
714 #define C66XX_EMIF16_RCSR_MOD_ID_IS_DEFAULT_VALUE			(C66XX_get_emif16_rcsr_mod_id() == C66XX_EMIF16_RCSR_MOD_ID_DEFAULT_VALUE)
715 #define C66XX_EMIF16_RCSR_MJ_REV_IS_DEFAULT_VALUE			(C66XX_get_emif16_rcsr_mj_rev() == C66XX_EMIF16_RCSR_MJ_REV_DEFAULT_VALUE)
716 #define C66XX_EMIF16_RCSR_MIN_REV_IS_DEFAULT_VALUE			(C66XX_get_emif16_rcsr_min_rev() == C66XX_EMIF16_RCSR_MIN_REV_DEFAULT_VALUE)
717 
718 
719 //------------ Async wait cycle config register macros ------------------------
720 #define C66XX_get_emif16_awccr_rg()							C66XX_GET_RG_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR)
721 #define C66XX_set_emif16_awccr_rg(v)						C66XX_SET_RG_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, v)
722 
723 	// dedicated bit specific macros
724 #define C66XX_get_emif16_awccr_wp1()						C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_WP1)
725 #define C66XX_set_emif16_awccr_wp1(v)						C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_WP1, v)
726 #define C66XX_get_emif16_awccr_wp0()						C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_WP0)
727 #define C66XX_set_emif16_awccr_wp0(v)						C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_WP0, v)
728 #define C66XX_get_emif16_awccr_cs5_wait()					C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS5_WAIT)
729 #define C66XX_set_emif16_awccr_cs5_wait(v)					C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS5_WAIT, v)
730 #define C66XX_get_emif16_awccr_cs4_wait()					C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS4_WAIT)
731 #define C66XX_set_emif16_awccr_cs4_wait(v)					C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS4_WAIT, v)
732 #define C66XX_get_emif16_awccr_cs3_wait()					C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS3_WAIT)
733 #define C66XX_set_emif16_awccr_cs3_wait(v)					C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS3_WAIT, v)
734 #define C66XX_get_emif16_awccr_cs2_wait()					C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS2_WAIT)
735 #define C66XX_set_emif16_awccr_cs2_wait(v)					C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS2_WAIT, v)
736 #define C66XX_get_emif16_awccr_max_ext_wait()				C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_MAX_EXT_WAIT)
737 #define C66XX_set_emif16_awccr_max_ext_wait(v)				C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_MAX_EXT_WAIT, v)
738 
739 	// direct bit set macros
740 #define C66XX_SET_EMIF16_AWCCR_WP1_ON						C66XX_set_emif16_awccr_wp1(C66XX_ON)
741 #define C66XX_SET_EMIF16_AWCCR_WP1_OFF						C66XX_set_emif16_awccr_wp1(C66XX_OFF)
742 #define C66XX_SET_EMIF16_AWCCR_WP0_ON						C66XX_set_emif16_awccr_wp0(C66XX_ON)
743 #define C66XX_SET_EMIF16_AWCCR_WP0_OFF						C66XX_set_emif16_awccr_wp0(C66XX_OFF)
744 #define C66XX_SET_EMIF16_AWCCR_CS5_WAIT1					C66XX_set_emif16_awccr_cs5_wait(C66XX_ON)
745 #define C66XX_SET_EMIF16_AWCCR_CS5_WAIT0					C66XX_set_emif16_awccr_cs5_wait(C66XX_OFF)
746 #define C66XX_SET_EMIF16_AWCCR_CS4_WAIT1					C66XX_set_emif16_awccr_cs4_wait(C66XX_ON)
747 #define C66XX_SET_EMIF16_AWCCR_CS4_WAIT0					C66XX_set_emif16_awccr_cs4_wait(C66XX_OFF)
748 #define C66XX_SET_EMIF16_AWCCR_CS3_WAIT1					C66XX_set_emif16_awccr_cs3_wait(C66XX_ON)
749 #define C66XX_SET_EMIF16_AWCCR_CS3_WAIT0					C66XX_set_emif16_awccr_cs3_wait(C66XX_OFF)
750 #define C66XX_SET_EMIF16_AWCCR_CS2_WAIT1					C66XX_set_emif16_awccr_cs2_wait(C66XX_ON)
751 #define C66XX_SET_EMIF16_AWCCR_CS2_WAIT0					C66XX_set_emif16_awccr_cs2_wait(C66XX_OFF)
752 
753 	// condition check macros (for use in IF() and other conditional operators)
754 #define C66XX_EMIF16_AWCCR_WP1_IS_ON						(C66XX_get_emif16_awccr_wp1() == C66XX_ON)
755 #define C66XX_EMIF16_AWCCR_WP0_IS_ON						(C66XX_get_emif16_awccr_wp0() == C66XX_ON)
756 #define C66XX_EMIF16_AWCCR_CS5_WAIT_IS_WAIT1				(C66XX_get_emif16_awccr_cs5_wait() == C66XX_ON)
757 #define C66XX_EMIF16_AWCCR_CS4_WAIT_IS_WAIT1				(C66XX_get_emif16_awccr_cs4_wait() == C66XX_ON)
758 #define C66XX_EMIF16_AWCCR_CS3_WAIT_IS_WAIT1				(C66XX_get_emif16_awccr_cs3_wait() == C66XX_ON)
759 #define C66XX_EMIF16_AWCCR_CS2_WAIT_IS_WAIT1				(C66XX_get_emif16_awccr_cs2_wait() == C66XX_ON)
760 
761 
762 //------------ Async config registers macros ----------------------------------
763 // i index corresonds to Async config registers number
764 #define C66XX_get_emif16_acr_rg_addr(i)						(C66XX_EMIF16_A1CR_RG_ADDR + i * 0x4)
765 #define C66XX_get_emif16_acr_rg(i)							C66XX_GET_RG_VALUE(C66XX_get_emif16_acr_rg_addr(i))
766 #define C66XX_set_emif16_acr_rg(i,v)						C66XX_SET_RG_VALUE(C66XX_get_emif16_acr_rg_addr(i), v)
767 
768 	// dedicated bit specific macros
769 #define C66XX_get_emif16_acr_ss(i)							C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_SS)
770 #define C66XX_set_emif16_acr_ss(i,v)						C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_SS, v)
771 #define C66XX_get_emif16_acr_ew(i)							C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_EW)
772 #define C66XX_set_emif16_acr_ew(i,v)						C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_EW, v)
773 #define C66XX_get_emif16_acr_w_setup(i)						C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_SETUP)
774 #define C66XX_set_emif16_acr_w_setup(i,v)					C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_SETUP, v)
775 #define C66XX_get_emif16_acr_w_strobe(i)					C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_STROBE)
776 #define C66XX_set_emif16_acr_w_strobe(i,v)					C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_STROBE, v)
777 #define C66XX_get_emif16_acr_w_hold(i)						C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_HOLD)
778 #define C66XX_set_emif16_acr_w_hold(i,v)					C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_HOLD, v)
779 #define C66XX_get_emif16_acr_r_setup(i)						C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_SETUP)
780 #define C66XX_set_emif16_acr_r_setup(i,v)					C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_SETUP, v)
781 #define C66XX_get_emif16_acr_r_strobe(i)					C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_STROBE)
782 #define C66XX_set_emif16_acr_r_strobe(i,v)					C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_STROBE, v)
783 #define C66XX_get_emif16_acr_r_hold(i)						C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_HOLD)
784 #define C66XX_set_emif16_acr_r_hold(i,v)					C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_HOLD, v)
785 #define C66XX_get_emif16_acr_ta(i)							C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_TA)
786 #define C66XX_set_emif16_acr_ta(i,v)						C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_TA, v)
787 #define C66XX_get_emif16_acr_asize(i)						C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_ASIZE)
788 #define C66XX_set_emif16_acr_asize(i,v)						C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_ASIZE, v)
789 
790 	// direct bit set macros
791 #define C66XX_SET_EMIF16_ACR_SS_ON(i)						C66XX_set_emif16_acr_ss(i, C66XX_ON)
792 #define C66XX_SET_EMIF16_ACR_SS_OFF(i)						C66XX_set_emif16_acr_ss(i, C66XX_OFF)
793 #define C66XX_SET_EMIF16_ACR_EW_ON(i)						C66XX_set_emif16_acr_ew(i, C66XX_ON)
794 #define C66XX_SET_EMIF16_ACR_EW_OFF(i)						C66XX_set_emif16_acr_ew(i, C66XX_OFF)
795 #define C66XX_SET_EMIF16_ACR_ASIZE_16BIT(i)					C66XX_set_emif16_acr_asize(i, C66XX_EMIF16_A1CR_ASIZE_16BIT)
796 #define C66XX_SET_EMIF16_ACR_ASIZE_8BIT(i)					C66XX_set_emif16_acr_asize(i, C66XX_EMIF16_A1CR_ASIZE_8BIT)
797 
798 	// condition check macros (for use in IF() and other conditional operators)
799 #define C66XX_EMIF16_ACR_SS_IS_ON(i)						(C66XX_get_emif16_acr_ss(i) == C66XX_ON)
800 #define C66XX_EMIF16_ACR_EW_IS_ON(i)						(C66XX_get_emif16_acr_ew(i) == C66XX_ON)
801 #define C66XX_EMIF16_ACR_ASIZE_IS_16BIT(i)					(C66XX_get_emif16_acr_asize(i) == C66XX_EMIF16_A1CR_ASIZE_16BIT)
802 
803 
804 //------------ Interrupt raw register macros ----------------------------------
805 #define C66XX_get_emif16_irr_rg()							C66XX_GET_RG_VALUE(C66XX_EMIF16_IRR_RG_ADDR)
806 #define C66XX_set_emif16_irr_rg(v)							C66XX_SET_RG_VALUE(C66XX_EMIF16_IRR_RG_ADDR, v)
807 
808 	// dedicated bit specific macros
809 #define C66XX_get_emif16_irr_wr()							C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IRR_RG_ADDR, EMIF16_IRR_WR)
810 #define C66XX_set_emif16_irr_wr(v)							C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IRR_RG_ADDR, EMIF16_IRR_WR, v)
811 #define C66XX_get_emif16_irr_at()							C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IRR_RG_ADDR, EMIF16_IRR_AT)
812 #define C66XX_set_emif16_irr_at(v)							C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IRR_RG_ADDR, EMIF16_IRR_AT, v)
813 
814 	// direct bit set macros
815 #define C66XX_CLEAR_EMIF16_IRR_AT							C66XX_set_emif16_irr_at(C66XX_ON)
816 
817 	// condition check macros (for use in IF() and other conditional operators)
818 #define C66XX_EMIF16_IRR_AT_IS_ON							(C66XX_get_emif16_irr_at() == C66XX_ON)
819 
820 
821 //------------ Interrupt masked register macros -------------------------------
822 #define C66XX_get_emif16_imr_rg()							C66XX_GET_RG_VALUE(C66XX_EMIF16_IMR_RG_ADDR)
823 #define C66XX_set_emif16_imr_rg(v)							C66XX_SET_RG_VALUE(C66XX_EMIF16_IMR_RG_ADDR, v)
824 
825 	// dedicated bit specific macros
826 #define C66XX_get_emif16_imr_wr_masked()					C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMR_RG_ADDR, EMIF16_IMR_WR_MASKED)
827 #define C66XX_set_emif16_imr_wr_masked(v)					C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMR_RG_ADDR, EMIF16_IMR_WR_MASKED, v)
828 #define C66XX_get_emif16_imr_at_masked()					C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMR_RG_ADDR, EMIF16_IMR_AT_MASKED)
829 #define C66XX_set_emif16_imr_at_masked(v)					C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMR_RG_ADDR, EMIF16_IMR_AT_MASKED, v)
830 
831 	// direct bit set macros
832 #define C66XX_CLEAR_EMIF16_IMR_AT_MASKED					C66XX_set_emif16_imr_at_masked(C66XX_ON)
833 
834 	// condition check macros (for use in IF() and other conditional operators)
835 #define C66XX_EMIF16_IMR_AT_MASKED_IS_ON					(C66XX_get_emif16_imr_at_masked() == C66XX_ON)
836 
837 
838 //------------ Interrupt mask set register macros -----------------------------
839 #define C66XX_get_emif16_imsr_rg()							C66XX_GET_RG_VALUE(C66XX_EMIF16_IMSR_RG_ADDR)
840 #define C66XX_set_emif16_imsr_rg(v)							C66XX_SET_RG_VALUE(C66XX_EMIF16_IMSR_RG_ADDR, v)
841 
842 	// dedicated bit specific macros
843 #define C66XX_get_emif16_imsr_wr_mask_set()					C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMSR_RG_ADDR, EMIF16_IMSR_WR_MASK_SET)
844 #define C66XX_set_emif16_imsr_wr_mask_set(v)				C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMSR_RG_ADDR, EMIF16_IMSR_WR_MASK_SET, v)
845 #define C66XX_get_emif16_imsr_at_mask_set()					C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMSR_RG_ADDR, EMIF16_IMSR_AT_MASK_SET)
846 #define C66XX_set_emif16_imsr_at_mask_set(v)				C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMSR_RG_ADDR, EMIF16_IMSR_AT_MASK_SET, v)
847 
848 	// direct bit set macros
849 #define C66XX_SET_EMIF16_IMSR_AT_MASK_SET_ON				C66XX_set_emif16_imsr_at_mask_set(C66XX_ON)
850 
851 	// condition check macros (for use in IF() and other conditional operators)
852 #define C66XX_EMIF16_IMSR_AT_MASK_SET_IS_ON					(C66XX_get_emif16_imsr_at_mask_set() == C66XX_ON)
853 
854 
855 //------------ Interrupt mask clear register macros -----------------------------
856 #define C66XX_get_emif16_imcr_rg()							C66XX_GET_RG_VALUE(C66XX_EMIF16_IMCR_RG_ADDR)
857 #define C66XX_set_emif16_imcr_rg(v)							C66XX_SET_RG_VALUE(C66XX_EMIF16_IMCR_RG_ADDR, v)
858 
859 	// dedicated bit specific macros
860 #define C66XX_get_emif16_imcr_wr_mask_clr()					C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMCR_RG_ADDR, EMIF16_IMCR_WR_MASK_CLR)
861 #define C66XX_set_emif16_imcr_wr_mask_clr(v)				C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMCR_RG_ADDR, EMIF16_IMCR_WR_MASK_CLR, v)
862 #define C66XX_get_emif16_imcr_at_mask_clr()					C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMCR_RG_ADDR, EMIF16_IMCR_AT_MASK_CLR)
863 #define C66XX_set_emif16_imcr_at_mask_clr(v)				C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMCR_RG_ADDR, EMIF16_IMCR_AT_MASK_CLR, v)
864 
865 	// direct bit set macros
866 #define C66XX_SET_EMIF16_IMCR_AT_MASK_CLR_ON				C66XX_set_emif16_imcr_at_mask_clr(C66XX_ON)
867 
868 	// condition check macros (for use in IF() and other conditional operators)
869 #define C66XX_EMIF16_IMCR_AT_MASK_CLR_IS_ON					(C66XX_get_emif16_imcr_at_mask_clr() == C66XX_ON)
870 //=============================================================================
871 
872 
873 
874 //=============================================================================
875 //============ Timer registers macros =========================================
876 //=============================================================================
877 
878 //------------ Emulation Management and Clock Speed register macros -----------
879 #define C66XX_get_timer_emumgt_clkspd_rg(timer)				C66XX_GET_RG_VALUE(C66XX_TIMER_EMUMGT_CLKSPD_RG_ADDR(timer))
880 
881 	// dedicated bit specific macros
882 #define C66XX_get_timer_emumgt_clkspd_clkdiv(timer)			C66XX_GET_FIELD_VALUE(C66XX_TIMER_EMUMGT_CLKSPD_RG_ADDR(timer), TIMER_EMUMGT_CLKSPD_CLKDIV)
883 
884 
885 //------------ Counter register low register macros ---------------------------
886 #define C66XX_get_timer_cntlo_rg(timer)						C66XX_GET_RG_VALUE(C66XX_TIMER_CNTLO_RG_ADDR(timer))
887 #define C66XX_set_timer_cntlo_rg(timer,v)					C66XX_SET_RG_VALUE(C66XX_TIMER_CNTLO_RG_ADDR(timer), v)
888 
889 
890 //------------ Counter register high register macros --------------------------
891 #define C66XX_get_timer_cnthi_rg(timer)						C66XX_GET_RG_VALUE(C66XX_TIMER_CNTHI_RG_ADDR(timer))
892 #define C66XX_set_timer_cnthi_rg(timer,v)					C66XX_SET_RG_VALUE(C66XX_TIMER_CNTHI_RG_ADDR(timer), v)
893 
894 
895 //------------ Period register low register macros ----------------------------
896 #define C66XX_get_timer_prdlo_rg(timer)						C66XX_GET_RG_VALUE(C66XX_TIMER_PRDLO_RG_ADDR(timer))
897 #define C66XX_set_timer_prdlo_rg(timer,v)					C66XX_SET_RG_VALUE(C66XX_TIMER_PRDLO_RG_ADDR(timer), v)
898 
899 
900 //------------ Period register high register macros ---------------------------
901 #define C66XX_get_timer_prdhi_rg(timer)						C66XX_GET_RG_VALUE(C66XX_TIMER_PRDHI_RG_ADDR(timer))
902 #define C66XX_set_timer_prdhi_rg(timer,v)					C66XX_SET_RG_VALUE(C66XX_TIMER_PRDHI_RG_ADDR(timer), v)
903 
904 
905 //------------ Timer control register macros ----------------------------------
906 #define C66XX_get_timer_tcr_rg(timer)						C66XX_GET_RG_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer))
907 #define C66XX_set_timer_tcr_rg(timer,v)						C66XX_SET_RG_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), v)
908 
909 	// dedicated bit specific macros
910 #define C66XX_get_timer_tcr_readrstmode_hi(timer)			C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_READRSTMODE_HI)
911 #define C66XX_set_timer_tcr_readrstmode_hi(timer,v)			C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_READRSTMODE_HI, v)
912 #define C66XX_get_timer_tcr_enamode_hi(timer)				C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_ENAMODE_HI)
913 #define C66XX_set_timer_tcr_enamode_hi(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_ENAMODE_HI, v)
914 #define C66XX_get_timer_tcr_pwid_hi(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_PWID_HI)
915 #define C66XX_set_timer_tcr_pwid_hi(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_PWID_HI, v)
916 #define C66XX_get_timer_tcr_cp_hi(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CP_HI)
917 #define C66XX_set_timer_tcr_cp_hi(timer,v)					C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CP_HI, v)
918 #define C66XX_get_timer_tcr_invoutp_hi(timer)				C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVOUTP_HI)
919 #define C66XX_set_timer_tcr_invoutp_hi(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVOUTP_HI, v)
920 #define C66XX_get_timer_tcr_tstat_hi(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_TSTAT_HI)
921 #define C66XX_get_timer_tcr_capevtmode_lo(timer)			C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CAPEVTMODE_LO)
922 #define C66XX_set_timer_tcr_capevtmode_lo(timer,v)			C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CAPEVTMODE_LO, v)
923 #define C66XX_get_timer_tcr_capmode_lo(timer)				C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CAPMODE_LO)
924 #define C66XX_set_timer_tcr_capmode_lo(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CAPMODE_LO, v)
925 #define C66XX_get_timer_tcr_readrstmode_lo(timer)			C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_READRSTMODE_LO)
926 #define C66XX_set_timer_tcr_readrstmode_lo(timer,v)			C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_READRSTMODE_LO, v)
927 #define C66XX_get_timer_tcr_tien_lo(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_TIEN_LO)
928 #define C66XX_set_timer_tcr_tien_lo(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_TIEN_LO, v)
929 #define C66XX_get_timer_tcr_clksrc_lo(timer)				C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CLKSRC_LO)
930 #define C66XX_set_timer_tcr_clksrc_lo(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CLKSRC_LO, v)
931 #define C66XX_get_timer_tcr_enamode_lo(timer)				C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_ENAMODE_LO)
932 #define C66XX_set_timer_tcr_enamode_lo(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_ENAMODE_LO, v)
933 #define C66XX_get_timer_tcr_pwid_lo(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_PWID_LO)
934 #define C66XX_set_timer_tcr_pwid_lo(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_PWID_LO, v)
935 #define C66XX_get_timer_tcr_cp_lo(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CP_LO)
936 #define C66XX_set_timer_tcr_cp_lo(timer,v)					C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CP_LO, v)
937 #define C66XX_get_timer_tcr_invinp_lo(timer)				C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVINP_LO)
938 #define C66XX_set_timer_tcr_invinp_lo(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVINP_LO, v)
939 #define C66XX_get_timer_tcr_invoutp_lo(timer)				C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVOUTP_LO)
940 #define C66XX_set_timer_tcr_invoutp_lo(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVOUTP_LO, v)
941 #define C66XX_get_timer_tcr_tstat_lo(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_TSTAT_LO)
942 
943 	// direct bit set macros
944 #define C66XX_SET_TIMER_TCR_READRSTMODE_HI_ON(timer)			C66XX_set_timer_tcr_readrstmode_hi(timer, C66XX_ON)
945 #define C66XX_SET_TIMER_TCR_READRSTMODE_HI_OFF(timer)			C66XX_set_timer_tcr_readrstmode_hi(timer, C66XX_OFF)
946 #define C66XX_SET_TIMER_TCR_ENAMODE_HI_DISABLED(timer)			C66XX_set_timer_tcr_enamode_hi(timer, C66XX_TIMER_TCR_ENAMODE_DISABLED)
947 #define C66XX_SET_TIMER_TCR_ENAMODE_HI_ONE_SHOT(timer)			C66XX_set_timer_tcr_enamode_hi(timer, C66XX_TIMER_TCR_ENAMODE_ONE_SHOT)
948 #define C66XX_SET_TIMER_TCR_ENAMODE_HI_CONT(timer)				C66XX_set_timer_tcr_enamode_hi(timer, C66XX_TIMER_TCR_ENAMODE_CONT)
949 #define C66XX_SET_TIMER_TCR_ENAMODE_HI_CONT_RELOAD(timer)		C66XX_set_timer_tcr_enamode_hi(timer, C66XX_TIMER_TCR_ENAMODE_CONT_RELOAD)
950 #define C66XX_SET_TIMER_TCR_PWID_HI_1_CLK(timer)				C66XX_set_timer_tcr_pwid_hi(timer, C66XX_TIMER_TCR_PWID_1_CLK)
951 #define C66XX_SET_TIMER_TCR_PWID_HI_2_CLK(timer)				C66XX_set_timer_tcr_pwid_hi(timer, C66XX_TIMER_TCR_PWID_2_CLK)
952 #define C66XX_SET_TIMER_TCR_PWID_HI_3_CLK(timer)				C66XX_set_timer_tcr_pwid_hi(timer, C66XX_TIMER_TCR_PWID_3_CLK)
953 #define C66XX_SET_TIMER_TCR_PWID_HI_4_CLK(timer)				C66XX_set_timer_tcr_pwid_hi(timer, C66XX_TIMER_TCR_PWID_4_CLK)
954 #define C66XX_SET_TIMER_TCR_CP_HI_ON(timer)						C66XX_set_timer_tcr_cp_hi(timer, C66XX_ON)
955 #define C66XX_SET_TIMER_TCR_CP_HI_OFF(timer)					C66XX_set_timer_tcr_cp_hi(timer, C66XX_OFF)
956 #define C66XX_SET_TIMER_TCR_INVOUTP_HI_ON(timer)				C66XX_set_timer_tcr_invoutp_hi(timer, C66XX_ON)
957 #define C66XX_SET_TIMER_TCR_INVOUTP_HI_OFF(timer)				C66XX_set_timer_tcr_invoutp_hi(timer, C66XX_OFF)
958 #define C66XX_SET_TIMER_TCR_CAPEVTMODE_LO_RISING_EDGE(timer)	C66XX_set_timer_tcr_capevtmode_lo(timer, C66XX_TIMER_TCR_CAPEVTMODE_RISING_EDGE)
959 #define C66XX_SET_TIMER_TCR_CAPEVTMODE_LO_FALLING_EDGE(timer)	C66XX_set_timer_tcr_capevtmode_lo(timer, C66XX_TIMER_TCR_CAPEVTMODE_FALLING_EDGE)
960 #define C66XX_SET_TIMER_TCR_CAPEVTMODE_LO_ANY_EDGE(timer)		C66XX_set_timer_tcr_capevtmode_lo(timer, C66XX_TIMER_TCR_CAPEVTMODE_ANY_EDGE)
961 #define C66XX_SET_TIMER_TCR_CAPMODE_LO_ON(timer)				C66XX_set_timer_tcr_capmode_lo(timer, C66XX_ON)
962 #define C66XX_SET_TIMER_TCR_CAPMODE_LO_OFF(timer)				C66XX_set_timer_tcr_capmode_lo(timer, C66XX_OFF)
963 #define C66XX_SET_TIMER_TCR_READRSTMODE_LO_ON(timer)			C66XX_set_timer_tcr_readrstmode_lo(timer, C66XX_ON)
964 #define C66XX_SET_TIMER_TCR_READRSTMODE_LO_OFF(timer)			C66XX_set_timer_tcr_readrstmode_lo(timer, C66XX_OFF)
965 #define C66XX_SET_TIMER_TCR_TIEN_LO_ON(timer)					C66XX_set_timer_tcr_tien_lo(timer, C66XX_ON)
966 #define C66XX_SET_TIMER_TCR_TIEN_LO_OFF(timer)					C66XX_set_timer_tcr_tien_lo(timer, C66XX_OFF)
967 #define C66XX_SET_TIMER_TCR_CLKSRC_LO_ON(timer)					C66XX_set_timer_tcr_clksrc_lo(timer, C66XX_ON)
968 #define C66XX_SET_TIMER_TCR_CLKSRC_LO_OFF(timer)				C66XX_set_timer_tcr_clksrc_lo(timer, C66XX_OFF)
969 #define C66XX_SET_TIMER_TCR_ENAMODE_LO_DISABLED(timer)			C66XX_set_timer_tcr_enamode_lo(timer, C66XX_TIMER_TCR_ENAMODE_DISABLED)
970 #define C66XX_SET_TIMER_TCR_ENAMODE_LO_ONE_SHOT(timer)			C66XX_set_timer_tcr_enamode_lo(timer, C66XX_TIMER_TCR_ENAMODE_ONE_SHOT)
971 #define C66XX_SET_TIMER_TCR_ENAMODE_LO_CONT(timer)				C66XX_set_timer_tcr_enamode_lo(timer, C66XX_TIMER_TCR_ENAMODE_CONT)
972 #define C66XX_SET_TIMER_TCR_ENAMODE_LO_CONT_RELOAD(timer)		C66XX_set_timer_tcr_enamode_lo(timer, C66XX_TIMER_TCR_ENAMODE_CONT_RELOAD)
973 #define C66XX_SET_TIMER_TCR_PWID_LO_1_CLK(timer)				C66XX_set_timer_tcr_pwid_lo(timer, C66XX_TIMER_TCR_PWID_1_CLK)
974 #define C66XX_SET_TIMER_TCR_PWID_LO_2_CLK(timer)				C66XX_set_timer_tcr_pwid_lo(timer, C66XX_TIMER_TCR_PWID_2_CLK)
975 #define C66XX_SET_TIMER_TCR_PWID_LO_3_CLK(timer)				C66XX_set_timer_tcr_pwid_lo(timer, C66XX_TIMER_TCR_PWID_3_CLK)
976 #define C66XX_SET_TIMER_TCR_PWID_LO_4_CLK(timer)				C66XX_set_timer_tcr_pwid_lo(timer, C66XX_TIMER_TCR_PWID_4_CLK)
977 #define C66XX_SET_TIMER_TCR_CP_LO_ON(timer)						C66XX_set_timer_tcr_cp_lo(timer, C66XX_ON)
978 #define C66XX_SET_TIMER_TCR_CP_LO_OFF(timer)					C66XX_set_timer_tcr_cp_lo(timer, C66XX_OFF)
979 #define C66XX_SET_TIMER_TCR_INVINP_LO_ON(timer)					C66XX_set_timer_tcr_invinp_lo(timer, C66XX_ON)
980 #define C66XX_SET_TIMER_TCR_INVINP_LO_OFF(timer)				C66XX_set_timer_tcr_invinp_lo(timer, C66XX_OFF)
981 #define C66XX_SET_TIMER_TCR_INVOUTP_LO_ON(timer)				C66XX_set_timer_tcr_invoutp_lo(timer, C66XX_ON)
982 #define C66XX_SET_TIMER_TCR_INVOUTP_LO_OFF(timer)				C66XX_set_timer_tcr_invoutp_lo(timer, C66XX_OFF)
983 
984 	// condition check macros (for use in IF() and other conditional operators)
985 #define C66XX_TIMER_TCR_READRSTMODE_HI_IS_ON(timer)				(C66XX_get_timer_tcr_readrstmode_hi(timer) == C66XX_ON)
986 #define C66XX_TIMER_TCR_ENAMODE_HI_IS_DISABLED(timer)			(C66XX_get_timer_tcr_enamode_hi(timer) == C66XX_TIMER_TCR_ENAMODE_DISABLED)
987 #define C66XX_TIMER_TCR_ENAMODE_HI_IS_ONE_SHOT(timer)			(C66XX_get_timer_tcr_enamode_hi(timer) == C66XX_TIMER_TCR_ENAMODE_ONE_SHOT)
988 #define C66XX_TIMER_TCR_ENAMODE_HI_IS_CONT(timer)				(C66XX_get_timer_tcr_enamode_hi(timer) == C66XX_TIMER_TCR_ENAMODE_CONT)
989 #define C66XX_TIMER_TCR_ENAMODE_HI_IS_CONT_RELOAD(timer)		(C66XX_get_timer_tcr_enamode_hi(timer) == C66XX_TIMER_TCR_ENAMODE_CONT_RELOAD)
990 #define C66XX_TIMER_TCR_PWI_HI_IS_1_CLK(timer)					(C66XX_get_timer_tcr_pwid_hi(timer) == C66XX_TIMER_TCR_PWID_1_CLK)
991 #define C66XX_TIMER_TCR_PWI_HI_IS_2_CLK(timer)					(C66XX_get_timer_tcr_pwid_hi(timer) == C66XX_TIMER_TCR_PWID_2_CLK)
992 #define C66XX_TIMER_TCR_PWI_HI_IS_3_CLK(timer)					(C66XX_get_timer_tcr_pwid_hi(timer) == C66XX_TIMER_TCR_PWID_3_CLK)
993 #define C66XX_TIMER_TCR_PWI_HI_IS_4_CLK(timer)					(C66XX_get_timer_tcr_pwid_hi(timer) == C66XX_TIMER_TCR_PWID_4_CLK)
994 #define C66XX_TIMER_TCR_CP_HI_IS_ON(timer)						(C66XX_get_timer_tcr_cp_hi(timer) == C66XX_ON)
995 #define C66XX_TIMER_TCR_INVOUTP_HI_IS_ON(timer)					(C66XX_get_timer_tcr_invoutp_hi(timer) == C66XX_ON)
996 #define C66XX_TIMER_TCR_TSTAT_HI_IS_ON(timer)					(C66XX_get_timer_tcr_tstat_hi(timer) == C66XX_ON)
997 #define C66XX_TIMER_TCR_CAPEVTMODE_LO_IS_RISING_EDGE(timer)		(C66XX_get_timer_tcr_capevtmode_lo(timer) == C66XX_TIMER_TCR_CAPEVTMODE_RISING_EDGE)
998 #define C66XX_TIMER_TCR_CAPEVTMODE_LO_IS_FALLING_EDGE(timer)	(C66XX_get_timer_tcr_capevtmode_lo(timer) == C66XX_TIMER_TCR_CAPEVTMODE_FALLING_EDGE)
999 #define C66XX_TIMER_TCR_CAPEVTMODE_LO_IS_ANY_EDGE(timer)		(C66XX_get_timer_tcr_capevtmode_lo(timer) == C66XX_TIMER_TCR_CAPEVTMODE_ANY_EDGE)
1000 #define C66XX_TIMER_TCR_CAPMODE_LO_IS_ON(timer)					(C66XX_get_timer_tcr_capmode_lo(timer) == C66XX_ON)
1001 #define C66XX_TIMER_TCR_READRSTMODE_LO_IS_ON(timer)				(C66XX_get_timer_tcr_readrstmode_lo(timer) == C66XX_ON)
1002 #define C66XX_TIMER_TCR_TIEN_LO_IS_ON(timer)					(C66XX_get_timer_tcr_tien_lo(timer) == C66XX_ON)
1003 #define C66XX_TIMER_TCR_CLKSRC_LO_IS_ON(timer)					(C66XX_get_timer_tcr_clksrc_lo(timer) == C66XX_ON)
1004 #define C66XX_TIMER_TCR_ENAMODE_LO_IS_DISABLED(timer)			(C66XX_get_timer_tcr_enamode_lo(timer) == C66XX_TIMER_TCR_ENAMODE_DISABLED)
1005 #define C66XX_TIMER_TCR_ENAMODE_LO_IS_ONE_SHOT(timer)			(C66XX_get_timer_tcr_enamode_lo(timer) == C66XX_TIMER_TCR_ENAMODE_ONE_SHOT)
1006 #define C66XX_TIMER_TCR_ENAMODE_LO_IS_CONT(timer)				(C66XX_get_timer_tcr_enamode_lo(timer) == C66XX_TIMER_TCR_ENAMODE_CONT)
1007 #define C66XX_TIMER_TCR_ENAMODE_LO_IS_CONT_RELOAD(timer)		(C66XX_get_timer_tcr_enamode_lo(timer) == C66XX_TIMER_TCR_ENAMODE_CONT_RELOAD)
1008 #define C66XX_TIMER_TCR_PWI_LO_IS_1_CLK(timer)					(C66XX_get_timer_tcr_pwid_lo(timer) == C66XX_TIMER_TCR_PWID_1_CLK)
1009 #define C66XX_TIMER_TCR_PWI_LO_IS_2_CLK(timer)					(C66XX_get_timer_tcr_pwid_lo(timer) == C66XX_TIMER_TCR_PWID_2_CLK)
1010 #define C66XX_TIMER_TCR_PWI_LO_IS_3_CLK(timer)					(C66XX_get_timer_tcr_pwid_lo(timer) == C66XX_TIMER_TCR_PWID_3_CLK)
1011 #define C66XX_TIMER_TCR_PWI_LO_IS_4_CLK(timer)					(C66XX_get_timer_tcr_pwid_lo(timer) == C66XX_TIMER_TCR_PWID_4_CLK)
1012 #define C66XX_TIMER_TCR_CP_LO_IS_ON(timer)						(C66XX_get_timer_tcr_cp_lo(timer) == C66XX_ON)
1013 #define C66XX_TIMER_TCR_INVINP_LO_IS_ON(timer)					(C66XX_get_timer_tcr_invinp_lo(timer) == C66XX_ON)
1014 #define C66XX_TIMER_TCR_INVOUTP_LO_IS_ON(timer)					(C66XX_get_timer_tcr_invoutp_lo(timer) == C66XX_ON)
1015 #define C66XX_TIMER_TCR_TSTAT_LO_IS_ON(timer)					(C66XX_get_timer_tcr_tstat_lo(timer) == C66XX_ON)
1016 
1017 
1018 //------------ Timer global control register macros ---------------------------
1019 #define C66XX_get_timer_tgcr_rg(timer)						C66XX_GET_RG_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer))
1020 #define C66XX_set_timer_tgcr_rg(timer,v)					C66XX_SET_RG_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), v)
1021 
1022 	// dedicated bit specific macros
1023 #define C66XX_get_timer_tgcr_tddrhi(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TDDRHI)
1024 #define C66XX_set_timer_tgcr_tddrhi(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TDDRHI, v)
1025 #define C66XX_get_timer_tgcr_pschi(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_PSCHI)
1026 #define C66XX_set_timer_tgcr_pschi(timer,v)					C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_PSCHI, v)
1027 #define C66XX_get_timer_tgcr_plusen(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_PLUSEN)
1028 #define C66XX_set_timer_tgcr_plusen(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_PLUSEN, v)
1029 #define C66XX_get_timer_tgcr_timmode(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMMODE)
1030 #define C66XX_set_timer_tgcr_timmode(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMMODE, v)
1031 #define C66XX_get_timer_tgcr_timhirs(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMHIRS)
1032 #define C66XX_set_timer_tgcr_timhirs(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMHIRS, v)
1033 #define C66XX_get_timer_tgcr_timlors(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMLORS)
1034 #define C66XX_set_timer_tgcr_timlors(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMLORS, v)
1035 
1036 	// direct bit set macros
1037 #define C66XX_SET_TIMER_TGCR_PLUSEN_ON(timer)				C66XX_set_timer_tgcr_plusen(timer, C66XX_ON)
1038 #define C66XX_SET_TIMER_TGCR_PLUSEN_OFF(timer)				C66XX_set_timer_tgcr_plusen(timer, C66XX_OFF)
1039 #define C66XX_SET_TIMER_TGCR_TIMMODE_64BIT_GPT(timer)		C66XX_set_timer_tgcr_timmode(timer, C66XX_TIMER_TGCR_TIMMODE_64BIT_GPT)
1040 #define C66XX_SET_TIMER_TGCR_TIMMODE_32BIT_UNCHAINED(timer)	C66XX_set_timer_tgcr_timmode(timer, C66XX_TIMER_TGCR_TIMMODE_32BIT_UNCHAINED)
1041 #define C66XX_SET_TIMER_TGCR_TIMMODE_64BIT_WDT(timer)		C66XX_set_timer_tgcr_timmode(timer, C66XX_TIMER_TGCR_TIMMODE_64BIT_WDT)
1042 #define C66XX_SET_TIMER_TGCR_TIMMODE_32BIT_CHAINED(timer)	C66XX_set_timer_tgcr_timmode(timer, C66XX_TIMER_TGCR_TIMMODE_32BIT_CHAINED)
1043 #define C66XX_SET_TIMER_TGCR_TIMHIRS_ON(timer)				C66XX_set_timer_tgcr_timhirs(timer, C66XX_ON)
1044 #define C66XX_SET_TIMER_TGCR_TIMHIRS_OFF(timer)				C66XX_set_timer_tgcr_timhirs(timer, C66XX_OFF)
1045 #define C66XX_SET_TIMER_TGCR_TIMLORS_ON(timer)				C66XX_set_timer_tgcr_timlors(timer, C66XX_ON)
1046 #define C66XX_SET_TIMER_TGCR_TIMLORS_OFF(timer)				C66XX_set_timer_tgcr_timlors(timer, C66XX_OFF)
1047 
1048 	// condition check macros (for use in IF() and other conditional operators)
1049 #define C66XX_TIMER_TGCR_PLUSEN_IS_ON(timer)				(C66XX_get_timer_tgcr_plusen(timer) == C66XX_ON)
1050 #define C66XX_TIMER_TGCR_TIMMODE_IS_64BIT_GPT(timer)		(C66XX_get_timer_tgcr_timmode(timer) == C66XX_TIMER_TGCR_TIMMODE_64BIT_GPT)
1051 #define C66XX_TIMER_TGCR_TIMMODE_IS_32BIT_UNCHAINED(timer)	(C66XX_get_timer_tgcr_timmode(timer) == C66XX_TIMER_TGCR_TIMMODE_32BIT_UNCHAINED)
1052 #define C66XX_TIMER_TGCR_TIMMODE_IS_64BIT_WDT(timer)		(C66XX_get_timer_tgcr_timmode(timer) == C66XX_TIMER_TGCR_TIMMODE_64BIT_WDT)
1053 #define C66XX_TIMER_TGCR_TIMMODE_IS_32BIT_CHAINED(timer)	(C66XX_get_timer_tgcr_timmode(timer) == C66XX_TIMER_TGCR_TIMMODE_32BIT_CHAINED)
1054 #define C66XX_TIMER_TGCR_TIMHIRS_IS_ON(timer)				(C66XX_get_timer_tgcr_timhirs(timer) == C66XX_ON)
1055 #define C66XX_TIMER_TGCR_TIMLORS_IS_ON(timer)				(C66XX_get_timer_tgcr_timlors(timer) == C66XX_ON)
1056 
1057 
1058 //------------ Watchdog Timer Control Register macros -------------------------
1059 #define C66XX_get_timer_wdtcr_rg(timer)						C66XX_GET_RG_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer))
1060 #define C66XX_set_timer_wdtcr_rg(timer,v)					C66XX_SET_RG_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), v)
1061 
1062 	// dedicated bit specific macros
1063 #define C66XX_get_timer_wdtcr_wdkey(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDKEY)
1064 #define C66XX_set_timer_wdtcr_wdkey(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDKEY, v)
1065 #define C66XX_get_timer_wdtcr_wdflag(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDFLAG)
1066 #define C66XX_set_timer_wdtcr_wdflag(timer,v)				C66XX_SET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDFLAG, v)
1067 #define C66XX_get_timer_wdtcr_wden(timer)					C66XX_GET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDEN)
1068 #define C66XX_set_timer_wdtcr_wden(timer,v)					C66XX_SET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDEN, v)
1069 
1070 	// direct bit set macros
1071 #define C66XX_SET_TIMER_WDTCR_WDKEY_FIRST_KEY(timer)		C66XX_set_timer_wdtcr_wdkey(timer, C66XX_TIMER_WDTCR_WDKEY_FIRST_KEY)
1072 #define C66XX_SET_TIMER_WDTCR_WDKEY_SECOND_KEY(timer)		C66XX_set_timer_wdtcr_wdkey(timer, C66XX_TIMER_WDTCR_WDKEY_SECOND_KEY)
1073 #define C66XX_SET_TIMER_WDTCR_WDFLAG_ON(timer)				C66XX_set_timer_wdtcr_wdflag(timer, C66XX_ON)
1074 #define C66XX_SET_TIMER_WDTCR_WDFLAG_OFF(timer)				C66XX_set_timer_wdtcr_wdflag(timer, C66XX_OFF)
1075 #define C66XX_SET_TIMER_WDTCR_WDEN_ON(timer)				C66XX_set_timer_wdtcr_wden(timer, C66XX_ON)
1076 #define C66XX_SET_TIMER_WDTCR_WDEN_OFF(timer)				C66XX_set_timer_wdtcr_wden(timer, C66XX_OFF)
1077 
1078 	// condition check macros (for use in IF() and other conditional operators)
1079 #define C66XX_TIMER_WDTCR_WDFLAG_IS_ON(timer)				(C66XX_get_timer_wdtcr_wdflag(timer) == C66XX_ON)
1080 #define C66XX_TIMER_WDTCR_WDEN_IS_ON(timer)					(C66XX_get_timer_wdtcr_wden(timer) == C66XX_ON)
1081 
1082 
1083 //------------ Timer Reload register low register macros ----------------------
1084 #define C66XX_get_timer_rello_rg(timer)						C66XX_GET_RG_VALUE(C66XX_TIMER_RELLO_RG_ADDR(timer))
1085 #define C66XX_set_timer_rello_rg(timer,v)					C66XX_SET_RG_VALUE(C66XX_TIMER_RELLO_RG_ADDR(timer), v)
1086 
1087 
1088 //------------ Timer Reload register high register macros ---------------------
1089 #define C66XX_get_timer_relhi_rg(timer)						C66XX_GET_RG_VALUE(C66XX_TIMER_RELHI_RG_ADDR(timer))
1090 #define C66XX_set_timer_relhi_rg(timer,v)					C66XX_SET_RG_VALUE(C66XX_TIMER_RELHI_RG_ADDR(timer), v)
1091 
1092 
1093 //------------ Timer Capture register low register macros ---------------------
1094 #define C66XX_get_timer_caplo_rg(timer)						C66XX_GET_RG_VALUE(C66XX_TIMER_CAPLO_RG_ADDR(timer))
1095 #define C66XX_set_timer_caplo_rg(timer,v)					C66XX_SET_RG_VALUE(C66XX_TIMER_CAPLO_RG_ADDR(timer), v)
1096 
1097 
1098 //------------ Timer Capture register high register macros --------------------
1099 #define C66XX_get_timer_caphi_rg(timer)						C66XX_GET_RG_VALUE(C66XX_TIMER_CAPHI_RG_ADDR(timer))
1100 #define C66XX_set_timer_caphi_rg(timer,v)					C66XX_SET_RG_VALUE(C66XX_TIMER_CAPHI_RG_ADDR(timer), v)
1101 
1102 
1103 //------------ Timer interrupt control and status register macros -------------
1104 #define C66XX_get_timer_intctlstat_rg(timer)				C66XX_GET_RG_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer))
1105 #define C66XX_set_timer_intctlstat_rg(timer,v)				C66XX_SET_RG_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), v)
1106 
1107 	// dedicated bit specific macros
1108 #define C66XX_get_timer_intctlstat_evtintstat_hi(timer)		C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTSTAT_HI)
1109 #define C66XX_set_timer_intctlstat_evtintstat_hi(timer,v)	C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTSTAT_HI, v)
1110 #define C66XX_get_timer_intctlstat_evtinten_hi(timer)		C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTEN_HI)
1111 #define C66XX_set_timer_intctlstat_evtinten_hi(timer,v)		C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTEN_HI, v)
1112 #define C66XX_get_timer_intctlstat_prdintstat_hi(timer)		C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTSTAT_HI)
1113 #define C66XX_set_timer_intctlstat_prdintstat_hi(timer,v)	C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTSTAT_HI, v)
1114 #define C66XX_get_timer_intctlstat_prdinten_hi(timer)		C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTEN_HI)
1115 #define C66XX_set_timer_intctlstat_prdinten_hi(timer,v)		C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTEN_HI, v)
1116 #define C66XX_get_timer_intctlstat_evtintstat_lo(timer)		C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTSTAT_LO)
1117 #define C66XX_set_timer_intctlstat_evtintstat_lo(timer,v)	C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTSTAT_LO, v)
1118 #define C66XX_get_timer_intctlstat_evtinten_lo(timer)		C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTEN_LO)
1119 #define C66XX_set_timer_intctlstat_evtinten_lo(timer,v)		C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTEN_LO, v)
1120 #define C66XX_get_timer_intctlstat_prdintstat_lo(timer)		C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTSTAT_LO)
1121 #define C66XX_set_timer_intctlstat_prdintstat_lo(timer,v)	C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTSTAT_LO, v)
1122 #define C66XX_get_timer_intctlstat_prdinten_lo(timer)		C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTEN_LO)
1123 #define C66XX_set_timer_intctlstat_prdinten_lo(timer,v)		C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTEN_LO, v)
1124 
1125 	// direct bit set macros
1126 #define C66XX_CLEAR_TIMER_INTCTLSTAT_EVTINTSTAT_HI(timer)	C66XX_set_timer_intctlstat_evtintstat_hi(timer, C66XX_ON)
1127 #define C66XX_SET_TIMER_INTCTLSTAT_EVTINTEN_HI_ON(timer)	C66XX_set_timer_intctlstat_evtinten_hi(timer, C66XX_ON)
1128 #define C66XX_SET_TIMER_INTCTLSTAT_EVTINTEN_HI_OFF(timer)	C66XX_set_timer_intctlstat_evtinten_hi(timer, C66XX_OFF)
1129 #define C66XX_CLEAR_TIMER_INTCTLSTAT_PRDINTSTAT_HI(timer)	C66XX_set_timer_intctlstat_prdintstat_hi(timer, C66XX_ON)
1130 #define C66XX_SET_TIMER_INTCTLSTAT_PRDINTEN_HI_ON(timer)	C66XX_set_timer_intctlstat_prdinten_hi(timer, C66XX_ON)
1131 #define C66XX_SET_TIMER_INTCTLSTAT_PRDINTEN_HI_OFF(timer)	C66XX_set_timer_intctlstat_prdinten_hi(timer, C66XX_OFF)
1132 #define C66XX_CLEAR_TIMER_INTCTLSTAT_EVTINTSTAT_LO(timer)	C66XX_set_timer_intctlstat_evtintstat_lo(timer, C66XX_ON)
1133 #define C66XX_SET_TIMER_INTCTLSTAT_EVTINTEN_LO_ON(timer)	C66XX_set_timer_intctlstat_evtinten_lo(timer, C66XX_ON)
1134 #define C66XX_SET_TIMER_INTCTLSTAT_EVTINTEN_LO_OFF(timer)	C66XX_set_timer_intctlstat_evtinten_lo(timer, C66XX_OFF)
1135 #define C66XX_CLEAR_TIMER_INTCTLSTAT_PRDINTSTAT_LO(timer)	C66XX_set_timer_intctlstat_prdintstat_lo(timer, C66XX_ON)
1136 #define C66XX_SET_TIMER_INTCTLSTAT_PRDINTEN_LO_ON(timer)	C66XX_set_timer_intctlstat_prdinten_lo(timer, C66XX_ON)
1137 #define C66XX_SET_TIMER_INTCTLSTAT_PRDINTEN_LO_OFF(timer)	C66XX_set_timer_intctlstat_prdinten_lo(timer, C66XX_OFF)
1138 
1139 	// condition check macros (for use in IF() and other conditional operators)
1140 #define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_HI_IS_ON(timer)	(C66XX_get_timer_intctlstat_evtintstat_hi(timer) == C66XX_ON)
1141 #define C66XX_TIMER_INTCTLSTAT_EVTINTEN_HI_IS_ON(timer)		(C66XX_get_timer_intctlstat_evtinten_hi(timer) == C66XX_ON)
1142 #define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_HI_IS_ON(timer)	(C66XX_get_timer_intctlstat_prdintstat_hi(timer) == C66XX_ON)
1143 #define C66XX_TIMER_INTCTLSTAT_PRDINTEN_HI_IS_ON(timer)		(C66XX_get_timer_intctlstat_prdinten_hi(timer) == C66XX_ON)
1144 #define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_LO_IS_ON(timer)	(C66XX_get_timer_intctlstat_evtintstat_lo(timer) == C66XX_ON)
1145 #define C66XX_TIMER_INTCTLSTAT_EVTINTEN_LO_IS_ON(timer)		(C66XX_get_timer_intctlstat_evtinten_lo(timer) == C66XX_ON)
1146 #define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_LO_IS_ON(timer)	(C66XX_get_timer_intctlstat_prdintstat_lo(timer) == C66XX_ON)
1147 #define C66XX_TIMER_INTCTLSTAT_PRDINTEN_LO_IS_ON(timer)		(C66XX_get_timer_intctlstat_prdinten_lo(timer) == C66XX_ON)
1148 
1149 //=============================================================================
1150 
1151 
1152 
1153 //=============================================================================
1154 #endif /* __C66XX_MACROS_HXX__ */
1155