Home
last modified time | relevance | path

Searched refs:Build (Results 1 – 25 of 686) sorted by relevance

12345678910>>...28

/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/gnu/src/
Dtx_thread_smp_initialize_wait.S96 LSL r10, r10, #2 @ Build offset to array indexes
101 LDR r3, =_tx_thread_system_state @ Build address of system state variable
102 ADD r3, r3, r10 @ Build index into the system state array
103 LDR r2, =0xF0F0F0F0 @ Build TX_INITIALIZE_IN_PROGRESS flag
111 LDR r2, =_tx_thread_smp_release_cores_flag @ Build address of release cores flag
122 LDR r3, =_tx_thread_system_state @ Build address of system state variable
123 ADD r3, r3, r10 @ Build index into the system state array
124 MOV r0, #0 @ Build clear value
129 … LDR r3, =_tx_thread_system_state @ Build address of system state variable of logical 0
Dtx_thread_schedule.S103 LSL r12, r10, #2 @ Build offset to array indexes
106 ADD r1, r1, r12 @ Build offset to execute ptr for this core
130 MOV r2, #172 @ Build offset to the lock
150 MOV r3, #0 @ Build clear value
164 MOV r3, #0 @ Build clear value for the lock
172 ADD r2, r2, r12 @ Build index into the current thread array
187 MOV r1, #0 @ Build clear value
212 ADD r2, r2, r12 @ Build index into the time-slice array
277 LSL r1, r1, #2 @ Build offset to array indexes
278 LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/gnu/src/
Dtx_thread_smp_initialize_wait.S96 LSL r10, r10, #2 @ Build offset to array indexes
101 LDR r3, =_tx_thread_system_state @ Build address of system state variable
102 ADD r3, r3, r10 @ Build index into the system state array
103 LDR r2, =0xF0F0F0F0 @ Build TX_INITIALIZE_IN_PROGRESS flag
111 LDR r2, =_tx_thread_smp_release_cores_flag @ Build address of release cores flag
122 LDR r3, =_tx_thread_system_state @ Build address of system state variable
123 ADD r3, r3, r10 @ Build index into the system state array
124 MOV r0, #0 @ Build clear value
129 … LDR r3, =_tx_thread_system_state @ Build address of system state variable of logical 0
Dtx_thread_schedule.S103 LSL r12, r10, #2 @ Build offset to array indexes
106 ADD r1, r1, r12 @ Build offset to execute ptr for this core
131 MOV r2, #172 @ Build offset to the lock
151 MOV r3, #0 @ Build clear value
165 MOV r3, #0 @ Build clear value for the lock
173 ADD r2, r2, r12 @ Build index into the current thread array
188 MOV r1, #0 @ Build clear value
212 ADD r2, r2, r12 @ Build index into the time-slice array
277 LSL r1, r1, #2 @ Build offset to array indexes
278 LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/ac5/src/
Dtx_thread_smp_initialize_wait.s94 LSL r10, r10, #2 ; Build offset to array indexes
99 LDR r3, =_tx_thread_system_state ; Build address of system state variable
100 ADD r3, r3, r10 ; Build index into the system state array
101 LDR r2, =0xF0F0F0F0 ; Build TX_INITIALIZE_IN_PROGRESS flag
109 LDR r2, =_tx_thread_smp_release_cores_flag ; Build address of release cores flag
120 LDR r3, =_tx_thread_system_state ; Build address of system state variable
121 ADD r3, r3, r10 ; Build index into the system state array
122 MOV r0, #0 ; Build clear value
127 … LDR r3, =_tx_thread_system_state ; Build address of system state variable of logical 0
Dtx_thread_schedule.s101 LSL r12, r10, #2 ; Build offset to array indexes
104 ADD r1, r1, r12 ; Build offset to execute ptr for this core
128 MOV r2, #172 ; Build offset to the lock
148 MOV r3, #0 ; Build clear value
162 MOV r3, #0 ; Build clear value for the lock
170 ADD r2, r2, r12 ; Build index into the current thread array
185 MOV r1, #0 ; Build clear value
210 ADD r2, r2, r12 ; Build index into the time-slice array
275 LSL r1, r1, #2 ; Build offset to array indexes
276 LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/ac5/src/
Dtx_thread_smp_initialize_wait.s94 LSL r10, r10, #2 ; Build offset to array indexes
99 LDR r3, =_tx_thread_system_state ; Build address of system state variable
100 ADD r3, r3, r10 ; Build index into the system state array
101 LDR r2, =0xF0F0F0F0 ; Build TX_INITIALIZE_IN_PROGRESS flag
109 LDR r2, =_tx_thread_smp_release_cores_flag ; Build address of release cores flag
120 LDR r3, =_tx_thread_system_state ; Build address of system state variable
121 ADD r3, r3, r10 ; Build index into the system state array
122 MOV r0, #0 ; Build clear value
127 … LDR r3, =_tx_thread_system_state ; Build address of system state variable of logical 0
Dtx_thread_schedule.s101 LSL r12, r10, #2 ; Build offset to array indexes
104 ADD r1, r1, r12 ; Build offset to execute ptr for this core
128 MOV r2, #172 ; Build offset to the lock
148 MOV r3, #0 ; Build clear value
162 MOV r3, #0 ; Build clear value for the lock
170 ADD r2, r2, r12 ; Build index into the current thread array
185 MOV r1, #0 ; Build clear value
210 ADD r2, r2, r12 ; Build index into the time-slice array
275 LSL r1, r1, #2 ; Build offset to array indexes
276 LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/gnu/src/
Dtx_thread_smp_initialize_wait.S96 LSL r10, r10, #2 @ Build offset to array indexes
101 LDR r3, =_tx_thread_system_state @ Build address of system state variable
102 ADD r3, r3, r10 @ Build index into the system state array
103 LDR r2, =0xF0F0F0F0 @ Build TX_INITIALIZE_IN_PROGRESS flag
111 LDR r2, =_tx_thread_smp_release_cores_flag @ Build address of release cores flag
122 LDR r3, =_tx_thread_system_state @ Build address of system state variable
123 ADD r3, r3, r10 @ Build index into the system state array
124 MOV r0, #0 @ Build clear value
129 … LDR r3, =_tx_thread_system_state @ Build address of system state variable of logical 0
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/src/
Dtx_thread_smp_initialize_wait.s94 LSL r10, r10, #2 ; Build offset to array indexes
99 LDR r3, =_tx_thread_system_state ; Build address of system state variable
100 ADD r3, r3, r10 ; Build index into the system state array
101 LDR r2, =0xF0F0F0F0 ; Build TX_INITIALIZE_IN_PROGRESS flag
109 LDR r2, =_tx_thread_smp_release_cores_flag ; Build address of release cores flag
120 LDR r3, =_tx_thread_system_state ; Build address of system state variable
121 ADD r3, r3, r10 ; Build index into the system state array
122 MOV r0, #0 ; Build clear value
127 … LDR r3, =_tx_thread_system_state ; Build address of system state variable of logical 0
Dtx_thread_schedule.s101 LSL r12, r10, #2 ; Build offset to array indexes
104 ADD r1, r1, r12 ; Build offset to execute ptr for this core
129 MOV r2, #172 ; Build offset to the lock
149 MOV r3, #0 ; Build clear value
163 MOV r3, #0 ; Build clear value for the lock
171 ADD r2, r2, r12 ; Build index into the current thread array
186 MOV r1, #0 ; Build clear value
210 ADD r2, r2, r12 ; Build index into the time-slice array
275 LSL r1, r1, #2 ; Build offset to array indexes
276 LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
[all …]
/ThreadX-v6.4.1/ports/cortex_m0/ac6/example_build/sample_threadx/
Dtx_initialize_low_level.S89 LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer
90 LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit @ Build first free address
96 @ LDR r0, =0xE0001000 @ Build address of DWT register
104 LDR r0, =0xE000E000 @ Build address of NVIC registers
106 ADD r0, r0, r2 @ Build vector base register
112 LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer
119 LDR r0, =0xE000E000 @ Build address of NVIC registers
122 LDR r1, =0x7 @ Build SysTick Control Enable Value
128 LDR r0, =0xE000E000 @ Build address of NVIC registers
133 LDR r0, =0xE000E000 @ Build address of NVIC registers
[all …]
/ThreadX-v6.4.1/ports/cortex_m0/iar/example_build/
Dtx_initialize_low_level.s98 LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer
103 ; LDR r0, =0xE0001000 ; Build address of DWT register
111 LDR r0, =0xE000E000 ; Build address of NVIC registers
113 ADD r0, r0, r2 ; Build vector base register
119 LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer
126 LDR r0, =0xE000E000 ; Build address of NVIC registers
129 MOVS r1, #0x7 ; Build SysTick Control Enable Value
135 LDR r0, =0xE000E000 ; Build address of NVIC registers
141 LDR r0, =0xE000E000 ; Build address of NVIC registers
148 LDR r0, =0xE000E000 ; Build address of NVIC registers
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/src/
Dtx_thread_smp_initialize_wait.S81 la $8, _tx_thread_smp_release_cores_flag # Build address of release cores flag
93 sll $8, $8, 2 # Build index based on VPE number
97 la $9, _tx_thread_system_state # Build address of system state variable
106 ori $8, $8, INITIAL_SR # Build initial SR
110 …la $8, _tx_thread_system_state # Build address of system state variable of logical VP…
/ThreadX-v6.4.1/ports/c667x/ccs/src/
Dtx_timer_interrupt.asm108 MVKL _tx_timer_system_clock,A0 ; Build address of system clock
111 MVKL _tx_timer_time_slice,A3 ; Build address of time slice
134 MVKL _tx_timer_expired_time_slice,A0 ; Build address of expired flag
151 MVKL _tx_timer_current_ptr,A2 ; Build address of current timer pointer
154 MVKL _tx_timer_expired,A3 ; Build address of expired flag
166 MVKL 1,A4 ; Build expired flag
181 MVKL _tx_timer_list_end,A3 ; Build timer list end address
184 MVKL _tx_timer_list_start,A3 ; Build timer list start address
207 MVKL _tx_timer_expired_time_slice,A3 ; Build time-slice expired flag
210 MVKL _tx_timer_expired,A0 ; Build timer expired flag
[all …]
/ThreadX-v6.4.1/ports/win32/vs_2019/example_build/
Dazure_rtos.sln21 {7342DEEF-AB3F-00D5-9EDB-2829CD277B76}.Debug|Win32.Build.0 = Debug|Win32
24 {7342DEEF-AB3F-00D5-9EDB-2829CD277B76}.Release|Win32.Build.0 = Release|Win32
27 {7342DEEF-AB3F-00D5-9EDB-2829CD277B76}.Template|Win32.Build.0 = Release|Win32
29 {7342DEEF-AB3F-00D5-9EDB-2829CD277B76}.Template|x64.Build.0 = Release|Win32
31 {51907112-62DA-98D6-7897-5A2FD48B99C3}.Debug|Win32.Build.0 = Debug|Win32
34 {51907112-62DA-98D6-7897-5A2FD48B99C3}.Release|Win32.Build.0 = Release|Win32
37 {51907112-62DA-98D6-7897-5A2FD48B99C3}.Template|Win32.Build.0 = Template|Win32
/ThreadX-v6.4.1/ports/cortex_m0/ac5/example_build/
Dtx_initialize_low_level.s141 LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer
142 LDR r1, =|Image$$ZI$$Limit| ; Build first free address
148 LDR r0, =0xE000ED08 ; Build address of NVIC registers
154 ; LDR r0, =0xE0001000 ; Build address of DWT register
162 LDR r0, =0xE000E000 ; Build address of NVIC registers
164 ADD r0, r0, r2 ; Build vector base register
170 LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer
177 LDR r0, =0xE000E000 ; Build address of NVIC registers
180 MOVS r1, #0x7 ; Build SysTick Control Enable Value
186 LDR r0, =0xE000E000 ; Build address of NVIC registers
[all …]
/ThreadX-v6.4.1/ports/cortex_m0/keil/example_build/
Dtx_initialize_low_level.s141 LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer
142 LDR r1, =|Image$$ZI$$Limit| ; Build first free address
148 LDR r0, =0xE000ED08 ; Build address of NVIC registers
154 ; LDR r0, =0xE0001000 ; Build address of DWT register
162 LDR r0, =0xE000E000 ; Build address of NVIC registers
164 ADD r0, r0, r2 ; Build vector base register
170 LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer
177 LDR r0, =0xE000E000 ; Build address of NVIC registers
180 MOVS r1, #0x7 ; Build SysTick Control Enable Value
186 LDR r0, =0xE000E000 ; Build address of NVIC registers
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m3/gnu/example_build/
Dtx_initialize_low_level.S93 LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer
94 LDR r1, =__RAM_segment_used_end__ @ Build first free address
99 MOV r0, #0xE000E000 @ Build address of NVIC registers
104 LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer
110 LDR r0, =0xE0001000 @ Build address of DWT register
116 MOV r0, #0xE000E000 @ Build address of NVIC registers
119 MOV r1, #0x7 @ Build SysTick Control Enable Value
/ThreadX-v6.4.1/ports/cortex_m0/gnu/example_build/
Dtx_initialize_low_level.S105 LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer
106 LDR r1, =__RAM_segment_used_end__ @ Build first free address
112 @ LDR r0, =0xE0001000 @ Build address of DWT register
120 LDR r0, =0xE000E000 @ Build address of NVIC registers
122 ADD r0, r0, r2 @ Build vector base register
128 LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer
135 LDR r0, =0xE000E000 @ Build address of NVIC registers
/ThreadX-v6.4.1/ports/cortex_m0/keil/src/
Dtx_thread_schedule.s95 MOVS r0, #0 ; Build value for TX_FALSE
96 LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
140 LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
141 LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address
142 MOVS r3, #0 ; Build NULL value
169 LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable
180 MOVS r5, #0 ; Build clear value
204 LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable
/ThreadX-v6.4.1/ports/cortex_m0/ac5/src/
Dtx_thread_schedule.s95 MOVS r0, #0 ; Build value for TX_FALSE
96 LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
140 LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
141 LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address
142 MOVS r3, #0 ; Build NULL value
169 LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable
180 MOVS r5, #0 ; Build clear value
203 LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable
/ThreadX-v6.4.1/ports/cortex_m0/gnu/src/
Dtx_thread_schedule.S101 MOVS r0, #0 @ Build value for TX_FALSE
102 LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag
153 LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address
154 LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address
155 MOVS r3, #0 @ Build NULL value
182 LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable
193 MOVS r5, #0 @ Build clear value
216 LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable
/ThreadX-v6.4.1/ports/cortex_m0/iar/src/
Dtx_thread_schedule.s93 MOVS r0, #0 ; Build value for TX_FALSE
94 LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
137 LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
138 LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address
139 MOVS r3, #0 ; Build NULL value
166 LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable
177 MOVS r5, #0 ; Build clear value
201 LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable
/ThreadX-v6.4.1/ports/cortex_m0/ac6/src/
Dtx_thread_schedule.S101 MOVS r0, #0 @ Build value for TX_FALSE
102 LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag
153 LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address
154 LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address
155 MOVS r3, #0 @ Build NULL value
182 LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable
193 MOVS r5, #0 @ Build clear value
216 LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable

12345678910>>...28