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/ThreadX-v6.3.0/ports_smp/arc_hs_smp/metaware/src/
Dtx_thread_stack_build.s147 mov r5, 0 ; Build initial clear value
148 st r5, [r3, 4] ; Store initial LP_START
149 st r5, [r3, 8] ; Store initial LP_END
150 st r5, [r3, 12] ; Store initial LP_COUNT
151 st r5, [r3, 16] ; Store initial blink
153 st r5, [r3, 24] ; Store initial fp (0 for backtrace)
155 st r5, [r3, 32] ; Store initial r25
156 st r5, [r3, 36] ; Store initial r24
157 st r5, [r3, 40] ; Store initial r23
158 st r5, [r3, 44] ; Store initial r22
[all …]
Dtx_thread_schedule.s140 llock r5, [r0]
141 breq r5, 0, _continue
144 add r5, r1, 1
145 scond r5, [r0]
160 …ld r5, [r0, 164] ; Pickup the ready bit for this thread to see …
161 breq r5, 0, _tx_thread_schedule_restart ; If not set, start over
186 ld r5, [r0, 24] ; Pickup time-slice for this thread
195 st r5, [r6] ; Setup time-slice
/ThreadX-v6.3.0/ports/arc_em/metaware/src/
Dtx_thread_stack_build.s143 mov r5, 0 ; Build initial clear value
144 st r5, [r3, 4] ; Store initial LP_START
145 st r5, [r3, 8] ; Store initial LP_END
146 st r5, [r3, 12] ; Store initial LP_COUNT
147 st r5, [r3, 16] ; Store initial blink
149 st r5, [r3, 24] ; Store initial fp (0 for backtrace)
151 st r5, [r3, 32] ; Store initial r25
152 st r5, [r3, 36] ; Store initial r24
153 st r5, [r3, 40] ; Store initial r23
154 st r5, [r3, 44] ; Store initial r22
[all …]
/ThreadX-v6.3.0/ports/arc_hs/metaware/src/
Dtx_thread_stack_build.s143 mov r5, 0 ; Build initial clear value
144 st r5, [r3, 4] ; Store initial LP_START
145 st r5, [r3, 8] ; Store initial LP_END
146 st r5, [r3, 12] ; Store initial LP_COUNT
147 st r5, [r3, 16] ; Store initial blink
149 st r5, [r3, 24] ; Store initial fp (0 for backtrace)
151 st r5, [r3, 32] ; Store initial r25
152 st r5, [r3, 36] ; Store initial r24
153 st r5, [r3, 40] ; Store initial r23
154 st r5, [r3, 44] ; Store initial r22
[all …]
Dtx_thread_register_bank_assign.s90 ld r5, [r4, 164] ; Pickup initial status32 from stack area
91 …or r5, r5, r2 ; Modify initial status32 with register bank n…
92 st r5, [r4, 164] ; Store initial status32 in stack area
105 mov r5, 3 ; Build type for hardware interrupt context
107 st r5, [r4, 0] ; Set stack frame type
/ThreadX-v6.3.0/ports/cortex_r5/ac5/example_build/
Dbuild_threadx.bat2 armasm -g --cpu=cortex-r5 --apcs=interwork tx_initialize_low_level.s
3 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_stack_build.s
4 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_schedule.s
5 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_system_return.s
6 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_context_save.s
7 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_context_restore.s
8 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_interrupt_control.s
9 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_timer_interrupt.s
10 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_fiq_context_restore.s
11 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_fiq_context_save.s
[all …]
/ThreadX-v6.3.0/ports/cortex_r5/gnu/example_build/
Dbuild_threadx.bat2 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 tx_initialize_low_level.S
3 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_stack_build.S
4 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_schedule.S
5 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_system_return.S
6 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_context_save.S
7 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_context_restore.S
8 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_interrupt_control.S
9 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_timer_interrupt.S
10 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_interrupt_disable.S
11 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_interrupt_restore.S
[all …]
Dbuild_threadx_sample.bat1 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 reset.S
2 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 crt0.S
3 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 tx_initialize_low_level.S
4 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc sample_threadx.c
5 arm-none-eabi-ld -A cortex-r5 -T sample_threadx.ld reset.o crt0.o tx_initialize_low_level.o sample_…
/ThreadX-v6.3.0/ports/cortex_m23/ac6/src/
Dtx_thread_schedule.S153 MOV r5, r9
159 MOV r5, lr // Copy lr to saveable register
160 STR r5, [r3] // Save lr on the stack
165 LDR r5, =0x90 // Secure stack index offset
166 LDR r5, [r1, r5] // Load secure stack index
167 CBZ r5, _skip_secure_save // Skip save if there is no secure context
178 LDR r5, [r4] // Pickup current time-slice
179 CBZ r5, __tx_ts_new // If not active, skip processing
183 STR r5, [r1, #24] // Save current time-slice
187 MOVW r5, #0 // Build clear value
[all …]
/ThreadX-v6.3.0/ports/cortex_m23/gnu/src/
Dtx_thread_schedule.S149 MOV r5, r9
155 MOV r5, lr // Copy lr to saveable register
156 STR r5, [r3] // Save lr on the stack
161 LDR r5, =0x90 // Secure stack index offset
162 LDR r5, [r1, r5] // Load secure stack index
163 CBZ r5, _skip_secure_save // Skip save if there is no secure context
174 LDR r5, [r4] // Pickup current time-slice
175 CBZ r5, __tx_ts_new // If not active, skip processing
179 STR r5, [r1, #24] // Save current time-slice
183 MOVW r5, #0 // Build clear value
[all …]
/ThreadX-v6.3.0/ports/cortex_m23/iar/src/
Dtx_thread_schedule.s148 MOV r5, r9
154 MOV r5, lr // Copy lr to saveable register
155 STR r5, [r3] // Save lr on the stack
160 LDR r5, =0x90 // Secure stack index offset
161 LDR r5, [r1, r5] // Load secure stack index
162 CBZ r5, _skip_secure_save // Skip save if there is no secure context
173 LDR r5, [r4] // Pickup current time-slice
174 CBZ r5, __tx_ts_new // If not active, skip processing
178 STR r5, [r1, #24] // Save current time-slice
182 MOVW r5, #0 // Build clear value
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m23/ac6/module_manager/src/
Dtx_thread_schedule.S157 STR r5, [r2, #52] // Save r5
256 MOV r5, r9
262 MOV r5, lr // Copy lr to saveable register
263 STR r5, [r3] // Save lr on the stack
268 LDR r5, =0xC4 // Secure stack index offset
269 LDR r5, [r1, r5] // Load secure stack index
270 CBZ r5, _skip_secure_save // Skip save if there is no secure context
281 LDR r5, [r4] // Pickup current time-slice
282 CBZ r5, __tx_ts_new // If not active, skip processing
286 STR r5, [r1, #24] // Save current time-slice
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m23/gnu/module_manager/src/
Dtx_thread_schedule.S153 STR r5, [r2, #52] // Save r5
252 MOV r5, r9
258 MOV r5, lr // Copy lr to saveable register
259 STR r5, [r3] // Save lr on the stack
264 LDR r5, =0xC4 // Secure stack index offset
265 LDR r5, [r1, r5] // Load secure stack index
266 CBZ r5, _skip_secure_save // Skip save if there is no secure context
277 LDR r5, [r4] // Pickup current time-slice
278 CBZ r5, __tx_ts_new // If not active, skip processing
282 STR r5, [r1, #24] // Save current time-slice
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m23/iar/module_manager/src/
Dtx_thread_schedule.s161 STR r5, [r2, #52] // Save r5
253 MOV r5, r9
259 MOV r5, lr // Copy lr to saveable register
260 STR r5, [r3] // Save lr on the stack
265 LDR r5, =0xC4 // Secure stack index offset
266 LDR r5, [r1, r5] // Load secure stack index
267 CBZ r5, _skip_secure_save // Skip save if there is no secure context
278 LDR r5, [r4] // Pickup current time-slice
279 CBZ r5, __tx_ts_new // If not active, skip processing
283 STR r5, [r1, #24] // Save current time-slice
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m0+/ac6/module_manager/src/
Dtx_thread_schedule.S145 STR r5, [r2, #52] // Save r5
238 MOV r5, r9 // Pick up r9
244 MOV r5, lr // Move lr into r5
245 STR r5, [r3] // Save lr
251 LDR r5, [r4] // Pickup current time-slice
252 CMP r5, #0
257 STR r5, [r1, #24] // Save current time-slice
325 LDR r5, [r1, #24] // Pickup thread's current time-slice
331 STR r5, [r4] // Setup global time-slice
345 MRS r5, CONTROL // Pickup current CONTROL register
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m0+/gnu/module_manager/src/
Dtx_thread_schedule.S145 STR r5, [r2, #52] // Save r5
238 MOV r5, r9 // Pick up r9
244 MOV r5, lr // Move lr into r5
245 STR r5, [r3] // Save lr
251 LDR r5, [r4] // Pickup current time-slice
252 CMP r5, #0
257 STR r5, [r1, #24] // Save current time-slice
325 LDR r5, [r1, #24] // Pickup thread's current time-slice
331 STR r5, [r4] // Setup global time-slice
345 MRS r5, CONTROL // Pickup current CONTROL register
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m0+/iar/module_manager/src/
Dtx_thread_schedule.S137 STR r5, [r2, #52] // Save r5
223 MOV r5, r9 // Pick up r9
229 MOV r5, lr // Move lr into r5
230 STR r5, [r3] // Save lr
236 LDR r5, [r4] // Pickup current time-slice
237 CMP r5, #0
242 STR r5, [r1, #24] // Save current time-slice
310 LDR r5, [r1, #24] // Pickup thread's current time-slice
316 STR r5, [r4] // Setup global time-slice
330 MRS r5, CONTROL // Pickup current CONTROL register
[all …]
/ThreadX-v6.3.0/ports/cortex_m0/ac5/src/
Dtx_thread_schedule.s171 LDR r5, [r4] ; Pickup current time-slice
172 CMP r5, #0 ; If not active, skip processing
177 STR r5, [r1, #24] ; Save current time-slice
181 MOVS r5, #0 ; Build clear value
182 STR r5, [r4] ; Clear time-slice
205 LDR r5, [r1, #24] ; Pickup thread's current time-slice
211 STR r5, [r4] ; Setup global time-slice
231 MOV r9,r5 ;
/ThreadX-v6.3.0/ports/cortex_m0/ac6/src/
Dtx_thread_schedule.S184 LDR r5, [r4] @ Pickup current time-slice
185 CMP r5, #0 @ If not active, skip processing
190 STR r5, [r1, #24] @ Save current time-slice
194 MOVS r5, #0 @ Build clear value
195 STR r5, [r4] @ Clear time-slice
218 LDR r5, [r1, #24] @ Pickup thread's current time-slice
224 STR r5, [r4] @ Setup global time-slice
244 MOV r9,r5 @
/ThreadX-v6.3.0/ports/cortex_m0/gnu/src/
Dtx_thread_schedule.S184 LDR r5, [r4] @ Pickup current time-slice
185 CMP r5, #0 @ If not active, skip processing
190 STR r5, [r1, #24] @ Save current time-slice
194 MOVS r5, #0 @ Build clear value
195 STR r5, [r4] @ Clear time-slice
218 LDR r5, [r1, #24] @ Pickup thread's current time-slice
224 STR r5, [r4] @ Setup global time-slice
244 MOV r9,r5 @
/ThreadX-v6.3.0/ports/cortex_m0/iar/src/
Dtx_thread_schedule.s168 LDR r5, [r4] ; Pickup current time-slice
169 CMP r5, #0 ; If not active, skip processing
174 STR r5, [r1, #24] ; Save current time-slice
178 MOVS r5, #0 ; Build clear value
179 STR r5, [r4] ; Clear time-slice
203 LDR r5, [r1, #24] ; Pickup thread's current time-slice
209 STR r5, [r4] ; Setup global time-slice
229 MOV r9,r5 ;
/ThreadX-v6.3.0/ports/cortex_m0/keil/src/
Dtx_thread_schedule.s171 LDR r5, [r4] ; Pickup current time-slice
172 CMP r5, #0 ; If not active, skip processing
177 STR r5, [r1, #24] ; Save current time-slice
181 MOVS r5, #0 ; Build clear value
182 STR r5, [r4] ; Clear time-slice
206 LDR r5, [r1, #24] ; Pickup thread's current time-slice
212 STR r5, [r4] ; Setup global time-slice
232 MOV r9,r5 ;
/ThreadX-v6.3.0/ports/cortex_r4/ac6/src/
Dtx_thread_schedule.S148 MOV r5, r0 // Save r0
150 MOV r0, r5 // Restore r0
159 LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR
162 MSR SPSR_cxsf, r5 // Setup SPSR for return
185 MSR CPSR_cxsf, r5 // Recover CPSR
Dtx_thread_system_return.S97 LDR r5, =_tx_thread_current_ptr // Pickup address of current ptr
98 LDR r6, [r5, #0] // Pickup current thread pointer
158 STR r4, [r5, #0] // Clear current thread pointer
/ThreadX-v6.3.0/ports_module/cortex_r4/ac6/module_manager/src/
Dtx_thread_system_return.S97 LDR r5, =_tx_thread_current_ptr // Pickup address of current ptr
98 LDR r6, [r5, #0] // Pickup current thread pointer
158 STR r4, [r5, #0] // Clear current thread pointer

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