Home
last modified time | relevance | path

Searched refs:r1 (Results 1 – 25 of 1440) sorted by relevance

12345678910>>...58

/ThreadX-v6.3.0/ports/cortex_a8/gnu/example_build/
DMP_GIC.s35 LDR r1, [r0] // Read the GIC Enable Register (ICDDCR)
36 ORR r1, r1, #0x01 // Set bit 0, the enable bit
37 STR r1, [r0] // Write the GIC Enable Register (ICDDCR)
52 LDR r1, [r0] // Read the GIC Enable Register (ICDDCR)
53 BIC r1, r1, #0x01 // Clear bit 0, the enable bit
54 STR r1, [r0] // Write the GIC Enable Register (ICDDCR)
67 MOV r1, r0 // Back up passed in ID value
73 MOV r2, r1 // Make working copy of ID in r2
79 AND r1, r1, #0x1F // Mask off to give offset within 32-bit block
81 MOV r3, r3, LSL r1 // Shift it left to position of ID
[all …]
/ThreadX-v6.3.0/ports/cortex_a7/gnu/example_build/
DMP_GIC.s35 LDR r1, [r0] // Read the GIC Enable Register (ICDDCR)
36 ORR r1, r1, #0x01 // Set bit 0, the enable bit
37 STR r1, [r0] // Write the GIC Enable Register (ICDDCR)
52 LDR r1, [r0] // Read the GIC Enable Register (ICDDCR)
53 BIC r1, r1, #0x01 // Clear bit 0, the enable bit
54 STR r1, [r0] // Write the GIC Enable Register (ICDDCR)
67 MOV r1, r0 // Back up passed in ID value
73 MOV r2, r1 // Make working copy of ID in r2
79 AND r1, r1, #0x1F // Mask off to give offset within 32-bit block
81 MOV r3, r3, LSL r1 // Shift it left to position of ID
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m23/ac6/module_manager/src/
Dtx_thread_schedule.S96 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
97 STR r1, [r0] //
104 LDR r1, =0xE000ED04 // Load ICSR address
105 STR r0, [r1] // Set PENDSVBIT in ICSR
131 LDR r1, [r0] // Pickup the current thread pointer
132 …STR r1, [r2, #0] // Save current thread pointer in fault info struc…
134 LDR r1, [r0] // Pickup SHCSR
135 STR r1, [r2, #8] // Save SHCSR
137 LDR r1, [r0] // Pickup CFSR
138 STR r1, [r2, #12] // Save CFSR
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m23/gnu/module_manager/src/
Dtx_thread_schedule.S92 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
93 STR r1, [r0] //
100 LDR r1, =0xE000ED04 // Load ICSR address
101 STR r0, [r1] // Set PENDSVBIT in ICSR
127 LDR r1, [r0] // Pickup the current thread pointer
128 …STR r1, [r2, #0] // Save current thread pointer in fault info struc…
130 LDR r1, [r0] // Pickup SHCSR
131 STR r1, [r2, #8] // Save SHCSR
133 LDR r1, [r0] // Pickup CFSR
134 STR r1, [r2, #12] // Save CFSR
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m23/iar/module_manager/src/
Dtx_thread_schedule.s102 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
103 STR r1, [r0] //
110 LDR r1, =0xE000ED04 // Load ICSR address
111 STR r0, [r1] // Set PENDSVBIT in ICSR
135 LDR r1, [r0] // Pickup the current thread pointer
136 …STR r1, [r2, #0] // Save current thread pointer in fault info struc…
138 LDR r1, [r0] // Pickup SHCSR
139 STR r1, [r2, #8] // Save SHCSR
141 LDR r1, [r0] // Pickup CFSR
142 STR r1, [r2, #12] // Save CFSR
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m0+/iar/example_build/
Dtx_initialize_low_level.s105 LDR r1, =__tx_free_memory_start // Build first free address
106 ADDS r1, r1, #4 //
107 STR r1, [r0] // Setup first unused memory pointer
112 LDR r1, =__vector_table // Pickup address of vector table
113 STR r1, [r0] // Set vector table address
118 LDR r1, =__vector_table // Pickup address of vector table
119 LDR r1, [r1] // Pickup reset stack pointer
120 STR r1, [r0] // Save system stack pointer
125 LDR r1, [r0] // Pickup the current value
127 ORRS r1, r1, r2 // Set the CYCCNTENA bit
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m0+/ac6/module_manager/src/
Dtx_thread_schedule.S99 LDR r1, =0xE000ED04 // Load ICSR address
100 STR r0, [r1] // Set PENDSVBIT in ICSR
131 LDR r1, [r0] // Pickup the current thread pointer
132 …STR r1, [r2, #0] // Save current thread pointer in fault info struc…
135 MRS r1, PSP // Pickup thread stack pointer
136 STR r1, [r2, #28] // Save thread stack pointer
137 …LDR r0, [r1] // Pickup saved r0 (as r0-r3, r12, lr, pc, xpsr ar…
139 LDR r0, [r1, #4] // Pickup saved r1
141 LDR r0, [r1, #8] // Pickup saved r2
156 LDR r0, [r1, #16] // Pickup saved r12
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m0+/gnu/module_manager/src/
Dtx_thread_schedule.S99 LDR r1, =0xE000ED04 // Load ICSR address
100 STR r0, [r1] // Set PENDSVBIT in ICSR
131 LDR r1, [r0] // Pickup the current thread pointer
132 …STR r1, [r2, #0] // Save current thread pointer in fault info struc…
135 MRS r1, PSP // Pickup thread stack pointer
136 STR r1, [r2, #28] // Save thread stack pointer
137 …LDR r0, [r1] // Pickup saved r0 (as r0-r3, r12, lr, pc, xpsr ar…
139 LDR r0, [r1, #4] // Pickup saved r1
141 LDR r0, [r1, #8] // Pickup saved r2
156 LDR r0, [r1, #16] // Pickup saved r12
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m0+/iar/module_manager/src/
Dtx_thread_schedule.S100 LDR r1, =0xE000ED04 // Load ICSR address
101 STR r0, [r1] // Set PENDSVBIT in ICSR
123 LDR r1, [r0] // Pickup the current thread pointer
124 …STR r1, [r2, #0] // Save current thread pointer in fault info struc…
127 MRS r1, PSP // Pickup thread stack pointer
128 STR r1, [r2, #28] // Save thread stack pointer
129 …LDR r0, [r1] // Pickup saved r0 (as r0-r3, r12, lr, pc, xpsr ar…
131 LDR r0, [r1, #4] // Pickup saved r1
133 LDR r0, [r1, #8] // Pickup saved r2
148 LDR r0, [r1, #16] // Pickup saved r12
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m7/ac5/module_manager/src/
Dtx_thread_schedule.s112 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
113 STR r1, [r0] //
121 MOV r1, #0xE000E000 // Load NVIC base
122 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
138 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
139 MSR BASEPRI, r1
148 LDR r1, [r0] // Pickup the current thread pointer
149 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
151 LDR r1, [r0] // Pickup SHCSR
152 STR r1, [r12, #8] // Save SHCSR
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m7/ac6/module_manager/src/
Dtx_thread_schedule.S114 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
115 STR r1, [r0] //
123 MOV r1, #0xE000E000 // Load NVIC base
124 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
147 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
148 MSR BASEPRI, r1
157 LDR r1, [r0] // Pickup the current thread pointer
158 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
160 LDR r1, [r0] // Pickup SHCSR
161 STR r1, [r12, #8] // Save SHCSR
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m7/gnu/module_manager/src/
Dtx_thread_schedule.S114 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
115 STR r1, [r0] //
123 MOV r1, #0xE000E000 // Load NVIC base
124 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
147 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
148 MSR BASEPRI, r1
157 LDR r1, [r0] // Pickup the current thread pointer
158 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
160 LDR r1, [r0] // Pickup SHCSR
161 STR r1, [r12, #8] // Save SHCSR
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m7/iar/module_manager/src/
Dtx_thread_schedule.s108 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
109 STR r1, [r0] //
117 MOV r1, #0xE000E000 // Load NVIC base
118 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
138 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
139 MSR BASEPRI, r1
148 LDR r1, [r0] // Pickup the current thread pointer
149 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
151 LDR r1, [r0] // Pickup SHCSR
152 STR r1, [r12, #8] // Save SHCSR
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m4/ac5/module_manager/src/
Dtx_thread_schedule.s112 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
113 STR r1, [r0] //
121 MOV r1, #0xE000E000 // Load NVIC base
122 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
138 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
139 MSR BASEPRI, r1
148 LDR r1, [r0] // Pickup the current thread pointer
149 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
151 LDR r1, [r0] // Pickup SHCSR
152 STR r1, [r12, #8] // Save SHCSR
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m4/ac6/module_manager/src/
Dtx_thread_schedule.S114 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
115 STR r1, [r0] //
123 MOV r1, #0xE000E000 // Load NVIC base
124 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
147 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
148 MSR BASEPRI, r1
157 LDR r1, [r0] // Pickup the current thread pointer
158 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
160 LDR r1, [r0] // Pickup SHCSR
161 STR r1, [r12, #8] // Save SHCSR
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m4/gnu/module_manager/src/
Dtx_thread_schedule.S114 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
115 STR r1, [r0] //
123 MOV r1, #0xE000E000 // Load NVIC base
124 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
147 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
148 MSR BASEPRI, r1
157 LDR r1, [r0] // Pickup the current thread pointer
158 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
160 LDR r1, [r0] // Pickup SHCSR
161 STR r1, [r12, #8] // Save SHCSR
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m4/iar/module_manager/src/
Dtx_thread_schedule.s108 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
109 STR r1, [r0] //
117 MOV r1, #0xE000E000 // Load NVIC base
118 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
138 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
139 MSR BASEPRI, r1
148 LDR r1, [r0] // Pickup the current thread pointer
149 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
151 LDR r1, [r0] // Pickup SHCSR
152 STR r1, [r12, #8] // Save SHCSR
[all …]
/ThreadX-v6.3.0/ports_arch/ARMv7-M/threadx_modules/ac5/module_manager/src/
Dtx_thread_schedule.s112 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
113 STR r1, [r0] //
121 MOV r1, #0xE000E000 // Load NVIC base
122 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
138 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
139 MSR BASEPRI, r1
148 LDR r1, [r0] // Pickup the current thread pointer
149 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
151 LDR r1, [r0] // Pickup SHCSR
152 STR r1, [r12, #8] // Save SHCSR
[all …]
/ThreadX-v6.3.0/ports_arch/ARMv7-M/threadx_modules/ac6/module_manager/src/
Dtx_thread_schedule.S114 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
115 STR r1, [r0] //
123 MOV r1, #0xE000E000 // Load NVIC base
124 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
147 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
148 MSR BASEPRI, r1
157 LDR r1, [r0] // Pickup the current thread pointer
158 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
160 LDR r1, [r0] // Pickup SHCSR
161 STR r1, [r12, #8] // Save SHCSR
[all …]
/ThreadX-v6.3.0/ports_arch/ARMv7-M/threadx_modules/gnu/module_manager/src/
Dtx_thread_schedule.S114 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
115 STR r1, [r0] //
123 MOV r1, #0xE000E000 // Load NVIC base
124 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
147 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
148 MSR BASEPRI, r1
157 LDR r1, [r0] // Pickup the current thread pointer
158 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
160 LDR r1, [r0] // Pickup SHCSR
161 STR r1, [r12, #8] // Save SHCSR
[all …]
/ThreadX-v6.3.0/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/
Dtx_thread_schedule.s108 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
109 STR r1, [r0] //
117 MOV r1, #0xE000E000 // Load NVIC base
118 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
138 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
139 MSR BASEPRI, r1
148 LDR r1, [r0] // Pickup the current thread pointer
149 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
151 LDR r1, [r0] // Pickup SHCSR
152 STR r1, [r12, #8] // Save SHCSR
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m3/ac5/module_manager/src/
Dtx_thread_schedule.s112 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
113 STR r1, [r0] //
121 MOV r1, #0xE000E000 // Load NVIC base
122 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
138 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
139 MSR BASEPRI, r1
148 LDR r1, [r0] // Pickup the current thread pointer
149 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
151 LDR r1, [r0] // Pickup SHCSR
152 STR r1, [r12, #8] // Save SHCSR
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m3/ac6/module_manager/src/
Dtx_thread_schedule.S114 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
115 STR r1, [r0] //
123 MOV r1, #0xE000E000 // Load NVIC base
124 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
147 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
148 MSR BASEPRI, r1
157 LDR r1, [r0] // Pickup the current thread pointer
158 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
160 LDR r1, [r0] // Pickup SHCSR
161 STR r1, [r12, #8] // Save SHCSR
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m3/gnu/module_manager/src/
Dtx_thread_schedule.S114 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
115 STR r1, [r0] //
123 MOV r1, #0xE000E000 // Load NVIC base
124 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
147 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
148 MSR BASEPRI, r1
157 LDR r1, [r0] // Pickup the current thread pointer
158 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
160 LDR r1, [r0] // Pickup SHCSR
161 STR r1, [r12, #8] // Save SHCSR
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m3/iar/module_manager/src/
Dtx_thread_schedule.s108 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
109 STR r1, [r0] //
117 MOV r1, #0xE000E000 // Load NVIC base
118 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
138 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
139 MSR BASEPRI, r1
148 LDR r1, [r0] // Pickup the current thread pointer
149 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
151 LDR r1, [r0] // Pickup SHCSR
152 STR r1, [r12, #8] // Save SHCSR
[all …]

12345678910>>...58