Searched refs:left (Results 1 – 25 of 58) sorted by relevance
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| /ThreadX-v6.3.0/ports_smp/cortex_a5x_smp/green/example_build/tgt/ |
| D | standalone_romcopy.ld | 49 // pulled into .boottext and left uncompressed.
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| /ThreadX-v6.3.0/ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/ |
| D | fvp_sse300_mps3_s.sct | 32 * executable region makes it only used the space left over by the ER_CODE
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| /ThreadX-v6.3.0/ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/SSE-300-MPS3/ |
| D | fvp_sse300_mps3_s.sct | 32 * executable region makes it only used the space left over by the ER_CODE
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| /ThreadX-v6.3.0/utility/rtos_compatibility_layers/FreeRTOS/ |
| D | tx_freertos.c | 2573 ULONG left; in vTimerSetReloadMode() local
2585 left = xTimer->timer.tx_timer_internal.tx_timer_internal_remaining_ticks; in vTimerSetReloadMode()
2588 ret = tx_timer_change(&xTimer->timer, left, xTimer->period); in vTimerSetReloadMode()
2590 ret = tx_timer_change(&xTimer->timer, left, 0u); in vTimerSetReloadMode()
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| /ThreadX-v6.3.0/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/ |
| D | startup.S | 258 ; Disable MPU and cache in case it was left enabled from an earlier run
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| /ThreadX-v6.3.0/ports_smp/cortex_a9_smp/ac5/ |
| D | readme_threadx.txt | 149 By default, Cortex-A9 FIQ interrupts are left alone by ThreadX. Of course, this
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| /ThreadX-v6.3.0/utility/benchmarks/thread_metric/ |
| D | thread_metric_readme.txt | 33 left in a suspended state. The lowest priority thread will resume
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| /ThreadX-v6.3.0/ports_smp/mips32_interaptiv_smp/green/example_build/ |
| D | init_vpe1.mip | 119 // and any TCs left over will be bound to the last a3_TC
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| /ThreadX-v6.3.0/ports_smp/cortex_a9_smp/gnu/ |
| D | readme_threadx.txt | 152 By default, Cortex-A9 FIQ interrupts are left alone by ThreadX. Of course, this
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| /ThreadX-v6.3.0/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/ |
| D | startup.s | 206 ; Disable caches and MMU in case they were left enabled from an earlier run
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| /ThreadX-v6.3.0/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/ |
| D | startup.s | 206 ; Disable caches, MMU and branch prediction in case they were left enabled from an earlier run
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| /ThreadX-v6.3.0/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/ |
| D | startup.s | 208 ; Disable caches and MMU in case they were left enabled from an earlier run
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| /ThreadX-v6.3.0/ports/cortex_a8/ac6/ |
| D | readme_threadx.txt | 214 By default, FIQ interrupts are left alone by ThreadX. Of course, this
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| /ThreadX-v6.3.0/ports/cortex_a9/ac6/ |
| D | readme_threadx.txt | 217 By default, FIQ interrupts are left alone by ThreadX. Of course, this
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| /ThreadX-v6.3.0/ports/cortex_r5/ac6/ |
| D | readme_threadx.txt | 217 By default, FIQ interrupts are left alone by ThreadX. Of course, this
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| /ThreadX-v6.3.0/ports/cortex_a15/ac6/ |
| D | readme_threadx.txt | 217 By default, FIQ interrupts are left alone by ThreadX. Of course, this
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| /ThreadX-v6.3.0/ports/cortex_a7/ac6/ |
| D | readme_threadx.txt | 217 By default, FIQ interrupts are left alone by ThreadX. Of course, this
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| /ThreadX-v6.3.0/ports_smp/cortex_a7_smp/gnu/ |
| D | readme_threadx.txt | 224 By default, Cortex-A7 FIQ interrupts are left alone by ThreadX. Of course, this
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| /ThreadX-v6.3.0/ports_smp/cortex_a5_smp/gnu/ |
| D | readme_threadx.txt | 224 By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this
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| /ThreadX-v6.3.0/ports_smp/cortex_a7_smp/ac5/ |
| D | readme_threadx.txt | 227 By default, Cortex-A7 FIQ interrupts are left alone by ThreadX. Of course, this
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| /ThreadX-v6.3.0/ports_smp/cortex_a9_smp/gnu/example_build/ |
| D | startup.S | 270 @; Disable caches, MMU and branch prediction in case they were left enabled from an earlier run
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| /ThreadX-v6.3.0/ports_smp/cortex_a5_smp/ac5/ |
| D | readme_threadx.txt | 227 By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this
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| /ThreadX-v6.3.0/ports_smp/cortex_a5_smp/gnu/example_build/ |
| D | startup.S | 270 @; Disable caches, MMU and branch prediction in case they were left enabled from an earlier run
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| /ThreadX-v6.3.0/ports_smp/cortex_a7_smp/gnu/example_build/ |
| D | startup.S | 252 @; Disable caches, MMU and branch prediction in case they were left enabled from an earlier run
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| /ThreadX-v6.3.0/ports/cortex_r4/ac6/ |
| D | readme_threadx.txt | 252 By default, Cortex-R4 FIQ interrupts are left alone by ThreadX. Of course, this
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