| /ThreadX-v6.3.0/ports_smp/mips32_interaptiv_smp/green/src/ |
| D | tx_thread_smp_initialize_wait.mip | 41 /* This function is the place where additional cores wait until */
79 /* Pickup the release cores flag. */
82 la $8, _tx_thread_smp_release_cores_flag # Build address of release cores flag
85 lw $9, ($8) # Pickup release cores flag
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| D | tx_thread_smp_low_level_initialize.mip | 46 /* number_of_cores Number of cores */
|
| /ThreadX-v6.3.0/ports_smp/mips32_interaptiv_smp/gnu/src/ |
| D | tx_thread_smp_initialize_wait.S | 82 la $8, _tx_thread_smp_release_cores_flag # Build address of release cores flag
85 lw $9, ($8) # Pickup release cores flag
|
| /ThreadX-v6.3.0/scripts/ |
| D | cmake_bootstrap.sh | 91 cores=$(nproc)
96 parallel_jobs=$(($cores / $build_counts))
|
| /ThreadX-v6.3.0/test/smp/cmake/ |
| D | run.sh | 91 cores=$(nproc)
96 parallel_jobs=$(($cores / $build_counts))
|
| /ThreadX-v6.3.0/test/tx/cmake/ |
| D | run.sh | 91 cores=$(nproc)
96 parallel_jobs=$(($cores / $build_counts))
|
| /ThreadX-v6.3.0/ports_arch/ARMv7-A/ |
| D | update.ps1 | 80 $cores = @("cortex_a5", "cortex_a7", "cortex_a8", "cortex_a9", "cortex_a12", "cortex_a15", "cortex_… variable
117 ForEach ($core in $cores) {
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| /ThreadX-v6.3.0/ports_arch/ARMv8-A/ |
| D | update.ps1 | 80 $cores = @("cortex_a35", "cortex_a53", "cortex_a55", "cortex_a57", "cortex_a65", "cortex_a65ae", "c… variable
122 ForEach ($core in $cores) {
|
| /ThreadX-v6.3.0/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/ |
| D | tx_boot.a64 | 112 // set cores 1-3 in reset state
115 orr w1, w1, #(7 << 1) // Hold cores 1-3 in reset
117 and w1, w1, #~(7 << 11) // Remove the power-on reset on cores 1-3
120 // set reset vector for cores 0-3
196 // enable hardware coherency between cores
218 // low level initialization for cores 1-3
|
| /ThreadX-v6.3.0/ports_smp/mips32_interaptiv_smp/green/example_build/ |
| D | demo_threadx_ram_interAptiv_3c2v4t.ghsmc | 4 # This is for a board with 3 cores, each with 4 TCs.
|
| D | join_domain.mip | 6 * For CPS cores join processing domain
62 // Enable coherence and allow interventions from all other cores.
64 li a0, 0x0f // Set Coherent domain enable for 4 cores
78 beqz a0, busy_wait_coherent_core // Busy wait on cores joining.
|
| /ThreadX-v6.3.0/ports_smp/cortex_a5x_smp/green/src/ |
| D | tx_thread_smp_initialize_wait.a64 | 51 /* This function is the place where additional cores wait until */
110 /* Pickup the release cores flag. */
112 LDR x4, =_tx_thread_smp_release_cores_flag // Build address of release cores flag
|
| D | tx_thread_smp_low_level_initialize.a64 | 55 /* number_of_cores Number of cores */
|
| /ThreadX-v6.3.0/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/ |
| D | MP_SCU.s | 27 AND r0, r0, #0x3 ; Bits 1:0 gives the number of cores-1
65 MOV r0, r0, LSR #4 ; Bits 7:4 gives the cores in SMP mode, shift then mask
77 ; cache and TLM maintenance operations to other SMP cores
|
| /ThreadX-v6.3.0/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/ |
| D | MP_SCU.s | 27 AND r0, r0, #0x3 ; Bits 1:0 gives the number of cores-1
65 MOV r0, r0, LSR #4 ; Bits 7:4 gives the cores in SMP mode, shift then mask
77 ; cache and TLM maintenance operations to other SMP cores
|
| /ThreadX-v6.3.0/ports_smp/cortex_a7_smp/gnu/src/ |
| D | tx_thread_smp_protection_wait_list_macros.h | 151 LDR r5, =_tx_thread_smp_protect_wait_list_size @ Load max cores address
152 LDR r5, [r5] @ Load max cores value
153 CMP r4, r5 @ Compare max cores to tail
|
| /ThreadX-v6.3.0/ports_smp/cortex_a7_smp/ac5/src/ |
| D | tx_thread_smp_protection_wait_list_macros.h | 155 LDR r5, =_tx_thread_smp_protect_wait_list_size ; Load max cores address
156 LDR r5, [r5] ; Load max cores value
157 CMP r4, r5 ; Compare max cores to tail
|
| D | tx_thread_smp_initialize_wait.s | 110 LDR r2, =_tx_thread_smp_release_cores_flag ; Build address of release cores flag
|
| /ThreadX-v6.3.0/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/ |
| D | MP_SCU.s | 45 AND r0, r0, #0x3 ; Bits 1:0 gives the number of cores
125 MOV r0, r0, LSR #4 ; Bits 7:4 gives the cores in SMP mode, shift then mask
137 ; cache and TLM maintenance operations to other SMP cores
|
| /ThreadX-v6.3.0/ports_smp/cortex_a9_smp/ac5/src/ |
| D | tx_thread_smp_protection_wait_list_macros.h | 155 LDR r5, =_tx_thread_smp_protect_wait_list_size ; Load max cores address
156 LDR r5, [r5] ; Load max cores value
157 CMP r4, r5 ; Compare max cores to tail
|
| /ThreadX-v6.3.0/ports_smp/cortex_a9_smp/gnu/src/ |
| D | tx_thread_smp_protection_wait_list_macros.h | 151 LDR r5, =_tx_thread_smp_protect_wait_list_size @ Load max cores address
152 LDR r5, [r5] @ Load max cores value
153 CMP r4, r5 @ Compare max cores to tail
|
| /ThreadX-v6.3.0/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/ |
| D | MP_SCU.s | 45 AND r0, r0, #0x3 ; Bits 1:0 gives the number of cores
125 MOV r0, r0, LSR #4 ; Bits 7:4 gives the cores in SMP mode, shift then mask
137 ; cache and TLM maintenance operations to other SMP cores
|
| /ThreadX-v6.3.0/ports_smp/cortex_a5_smp/gnu/src/ |
| D | tx_thread_smp_protection_wait_list_macros.h | 151 LDR r5, =_tx_thread_smp_protect_wait_list_size @ Load max cores address
152 LDR r5, [r5] @ Load max cores value
153 CMP r4, r5 @ Compare max cores to tail
|
| /ThreadX-v6.3.0/ports_smp/cortex_a5_smp/ac5/src/ |
| D | tx_thread_smp_protection_wait_list_macros.h | 155 LDR r5, =_tx_thread_smp_protect_wait_list_size ; Load max cores address
156 LDR r5, [r5] ; Load max cores value
157 CMP r4, r5 ; Compare max cores to tail
|
| /ThreadX-v6.3.0/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/ |
| D | crt1cl.s | 80 ; Note: this is setup for 2 cores and needs to be augmented if more than 2 cores
|
