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/ThreadX-v6.3.0/common/inc/
Dtx_thread.h74 #define TX_MOD32_BIT_SET(a,b) (b) = (((ULONG) 1) << ((a)%((UINT)32))); argument
79 #define TX_MOD32_BIT_SET(a,b) (b) = (((ULONG) 1) << ((a))); argument
89 #define TX_DIV32_BIT_SET(a,b) (b) = (((ULONG) 1) << ((a)/((UINT) 32))); argument
98 #define TX_THREAD_STATE_CHANGE(a, b) argument
156 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) \ argument
157 (b) = ((ULONG) 0); \
164 (b) = (b) + ((ULONG) 2); \
166 (b) = (b) + ((m) >> ((ULONG) 1)); \
171 (b) = (b) + ((ULONG) 4); \
175 (b) = (b) + ((ULONG) 2); \
[all …]
/ThreadX-v6.3.0/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/
Dtx_initialize_low_level.s118 b _tx_memory_error
126 b _tx_instruction_error
134 b _tx_ev_machine_check
142 b _tx_ev_tblmiss_inst
150 b _tx_ev_tblmiss_data
158 b _tx_ev_protection_viol
166 b _tx_ev_privilege_viol
174 b _tx_ev_software_int
182 b _tx_ev_trap
190 b _tx_ev_extension
[all …]
/ThreadX-v6.3.0/ports/arc_hs/metaware/example_build/sample_threadx/
Dtx_initialize_low_level.s170 b _tx_memory_error
178 b _tx_instruction_error
186 b _tx_ev_machine_check
194 b _tx_ev_tblmiss_inst
202 b _tx_ev_tblmiss_data
210 b _tx_ev_protection_viol
218 b _tx_ev_privilege_viol
226 b _tx_ev_software_int
234 b _tx_ev_trap
242 b _tx_ev_extension
[all …]
/ThreadX-v6.3.0/ports/arc_em/metaware/example_build/sample_threadx/
Dtx_initialize_low_level.s201 b _tx_memory_error
209 b _tx_instruction_error
217 b _tx_ev_machine_check
225 b _tx_ev_tblmiss_inst
233 b _tx_ev_tblmiss_data
241 b _tx_ev_protection_viol
249 b _tx_ev_privilege_viol
257 b _tx_ev_software_int
265 b _tx_ev_trap
273 b _tx_ev_extension
[all …]
/ThreadX-v6.3.0/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/
Dtx_boot.a6450 b _boot
53 b .
56 b .
59 b .
62 b .
65 b __tx_irq_handler
68 b .
71 b .
74 b .
77 b .
[all …]
/ThreadX-v6.3.0/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports_module/cortex_a35/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports/cortex_a75/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports/cortex_a76/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports/cortex_a76ae/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports/cortex_a76ae/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports/cortex_a77/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports/cortex_a77/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports/cortex_a76/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.3.0/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others

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