| /ThreadX-v6.3.0/ports_module/cortex_r4/ac6/module_manager/src/ |
| D | txm_module_manager_thread_stack_build.S | 24 #define THUMB_MASK 0x20 // THUMB bit macro
134 ORRNE r3, r3, #THUMB_MASK // Set T bit if set
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| D | tx_thread_context_restore.S | 38 #define THUMB_MASK 0x20 // Thumb bit mask macro
247 BIC r1, r1, #THUMB_MASK // Clear thumb bit
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| D | tx_thread_schedule.S | 42 #define THUMB_MASK 0x20 // Thumb bit (5) of CPSR/SPSR. macro
124 TST r0, #THUMB_MASK // Occurred in Thumb state?
418 ORRNE r2, r2, #THUMB_MASK // If so, set Thumb bit
419 BICEQ r2, r2, #THUMB_MASK // If not, clear Thumb bit
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| /ThreadX-v6.3.0/ports_module/cortex_a7/gnu/module_manager/src/ |
| D | tx_thread_stack_build.s | 33 THUMB_MASK = 0x20 define
136 …ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflec…
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| D | txm_module_manager_thread_stack_build.s | 30 #define THUMB_MASK 0x20 // THUMB bit macro
151 ORRNE r3, #THUMB_MASK // Set T bit if set
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| D | tx_thread_schedule.s | 43 #define THUMB_MASK 0x20 // Thumb bit mask macro
133 TST r0, #THUMB_MASK // Occurred in Thumb state?
176 TST r0, #THUMB_MASK // Check if we come from Thumb mode or ARM mode
226 TST r0, #THUMB_MASK // Check if we come from Thumb mode or ARM mode
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| /ThreadX-v6.3.0/ports_module/cortex_a7/ac5/module_manager/src/ |
| D | tx_thread_stack_build.s | 41 THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR define
147 BIC r3, r3, #THUMB_MASK ; Clear Thumb bit by default
150 ORREQ r3, r3, #THUMB_MASK ; Yes, set the Thumb bit
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| D | txm_module_manager_thread_stack_build.s | 33 THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR define
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| /ThreadX-v6.3.0/ports_module/cortex_r4/iar/module_manager/src/ |
| D | txm_module_manager_thread_stack_build.s | 24 THUMB_MASK DEFINE 0x20 ; THUMB bit label
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| D | tx_thread_context_restore.s | 29 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
224 BIC r1, r1, #THUMB_MASK ; Clear thumb bit - slarson
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| /ThreadX-v6.3.0/ports_module/cortex_a7/iar/module_manager/src/ |
| D | tx_thread_stack_build.s | 31 THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR define
128 …ORRNE r3, #THUMB_MASK ; If the initial PC is a thumb function, CPSR must reflect…
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| D | txm_module_manager_thread_stack_build.s | 24 THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR define
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| /ThreadX-v6.3.0/ports/cortex_r4/iar/src/ |
| D | tx_thread_context_restore.s | 38 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
200 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
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| /ThreadX-v6.3.0/ports/cortex_r5/iar/src/ |
| D | tx_thread_context_restore.s | 38 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
200 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
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| /ThreadX-v6.3.0/ports_module/cortex_r4/ac6/example_build/sample_threadx/ |
| D | tx_initialize_low_level.S | 36 #define THUMB_MASK 0x20 // Thumb bit (5) of CPSR/SPSR macro
445 BIC r0, r0, #THUMB_MASK // Clear THUMB mode
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| /ThreadX-v6.3.0/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/ |
| D | tx_initialize_low_level.S | 36 #define THUMB_MASK 0x20 // Thumb bit (5) of CPSR/SPSR macro
445 BIC r0, r0, #THUMB_MASK // Clear THUMB mode
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| /ThreadX-v6.3.0/ports_module/cortex_a7/gnu/example_build/ |
| D | tx_initialize_low_level.s | 37 THUMB_MASK = 0x20 // THUMB mode bit define
418 BIC r0, r0, #THUMB_MASK // Clear THUMB mode
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| /ThreadX-v6.3.0/ports/arm11/iar/src/ |
| D | tx_thread_context_restore.s | 42 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
198 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
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| /ThreadX-v6.3.0/ports/arm9/ac5/src/ |
| D | tx_thread_context_restore.s | 42 THUMB_MASK EQU 0x20 ; Thumb bit mask define
199 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
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| /ThreadX-v6.3.0/ports/arm9/iar/src/ |
| D | tx_thread_context_restore.s | 41 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
196 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
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| /ThreadX-v6.3.0/ports/arm11/ac5/src/ |
| D | tx_thread_context_restore.s | 42 THUMB_MASK EQU 0x20 ; Thumb bit mask define
199 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
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| /ThreadX-v6.3.0/ports/cortex_a9/iar/src/ |
| D | tx_thread_context_restore.s | 41 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
213 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
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| /ThreadX-v6.3.0/ports/cortex_a8/iar/src/ |
| D | tx_thread_context_restore.s | 41 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
213 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
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| /ThreadX-v6.3.0/ports/cortex_a7/iar/src/ |
| D | tx_thread_context_restore.s | 41 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
213 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
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| /ThreadX-v6.3.0/ports/cortex_a5/iar/src/ |
| D | tx_thread_context_restore.s | 41 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
215 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
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