| /ThreadX-v6.3.0/ports_module/cortex_a7/gnu/example_build/ |
| D | reset.S | 42 LDR pc, SWI // Software interrupt handler
53 SWI: label
|
| /ThreadX-v6.3.0/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/ |
| D | reset.S | 42 LDR pc, SWI // Software interrupt handler
53 SWI: label
|
| /ThreadX-v6.3.0/ports/cortex_a8/gnu/example_build/ |
| D | reset.S | 42 LDR pc, SWI // Software interrupt handler
53 SWI: label
|
| /ThreadX-v6.3.0/ports/cortex_a9/gnu/example_build/ |
| D | reset.S | 42 LDR pc, SWI // Software interrupt handler
53 SWI: label
|
| /ThreadX-v6.3.0/ports/cortex_a15/gnu/example_build/ |
| D | reset.S | 42 LDR pc, SWI // Software interrupt handler
53 SWI: label
|
| /ThreadX-v6.3.0/ports/cortex_a17/gnu/example_build/ |
| D | reset.S | 42 LDR pc, SWI // Software interrupt handler
53 SWI: label
|
| /ThreadX-v6.3.0/ports/cortex_a7/gnu/example_build/ |
| D | reset.S | 42 LDR pc, SWI // Software interrupt handler
53 SWI: label
|
| /ThreadX-v6.3.0/ports/cortex_a12/gnu/example_build/ |
| D | reset.S | 42 LDR pc, SWI // Software interrupt handler
53 SWI: label
|
| /ThreadX-v6.3.0/ports/cortex_a5/gnu/example_build/ |
| D | reset.S | 42 LDR pc, SWI // Software interrupt handler
53 SWI: label
|
| /ThreadX-v6.3.0/ports/cortex_r4/gnu/example_build/ |
| D | reset.S | 54 LDR pc, SWI @ Software interrupt handler
65 SWI: label
|
| /ThreadX-v6.3.0/ports/cortex_r5/gnu/example_build/ |
| D | reset.S | 54 LDR pc, SWI @ Software interrupt handler
65 SWI: label
|
| /ThreadX-v6.3.0/ports/arm11/gnu/example_build/ |
| D | reset.S | 54 LDR pc, SWI @ Software interrupt handler
65 SWI: label
|
| /ThreadX-v6.3.0/ports/arm9/gnu/example_build/ |
| D | reset.S | 54 LDR pc, SWI @ Software interrupt handler
65 SWI: label
|
| /ThreadX-v6.3.0/ports/cortex_a8/ghs/example_build/ |
| D | reset.arm | 11 LDR pc,SWI # Software interrupt handler
30 SWI:
|
| /ThreadX-v6.3.0/ports/cortex_a9/ghs/example_build/ |
| D | reset.arm | 11 LDR pc,SWI # Software interrupt handler
30 SWI:
|
| /ThreadX-v6.3.0/ports/cortex_r5/ghs/example_build/ |
| D | reset.arm | 11 LDR pc,SWI # Software interrupt handler
30 SWI:
|
| /ThreadX-v6.3.0/ports/cortex_r7/ghs/example_build/ |
| D | reset.arm | 11 LDR pc,SWI # Software interrupt handler
30 SWI:
|
| /ThreadX-v6.3.0/ports/cortex_r4/ghs/example_build/ |
| D | reset.arm | 11 LDR pc,SWI # Software interrupt handler
30 SWI:
|
| /ThreadX-v6.3.0/ports/cortex_a7/ghs/example_build/ |
| D | reset.arm | 11 LDR pc,SWI # Software interrupt handler
30 SWI:
|
| /ThreadX-v6.3.0/ports/cortex_a5/ghs/example_build/ |
| D | reset.arm | 11 LDR pc,SWI # Software interrupt handler
30 SWI:
|
| /ThreadX-v6.3.0/ports/cortex_a9/iar/example_build/ |
| D | cstartup.s | 47 LDR PC,SWI_Addr ; Software interrupt (SWI/SVC)
|
| /ThreadX-v6.3.0/ports_module/cortex_a7/iar/example_build/ |
| D | cstartup.s | 47 LDR PC,SWI_Addr ; Software interrupt (SWI/SVC)
|
| /ThreadX-v6.3.0/ports_arch/ARMv7-A/threadx/ports/iar/example_build/ |
| D | cstartup.s | 47 LDR PC,SWI_Addr ; Software interrupt (SWI/SVC)
|
| /ThreadX-v6.3.0/ports/cortex_a8/iar/example_build/ |
| D | cstartup.s | 47 LDR PC,SWI_Addr ; Software interrupt (SWI/SVC)
|
| /ThreadX-v6.3.0/ports/cortex_a15/iar/example_build/ |
| D | cstartup.s | 47 LDR PC,SWI_Addr ; Software interrupt (SWI/SVC)
|
