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Searched refs:GIC_CPU_BASEADDR (Results 1 – 1 of 1) sorted by relevance

/ThreadX-v6.3.0/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/
Dtx_zynqmp_low_level.c54 #define GIC_CPU_BASEADDR (CBAR+0x20000ull) macro
55 #define GIC_CPU_REG(offset) *((volatile uint32_t *)(GIC_CPU_BASEADDR+offset))