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Searched refs:GICD_ICFGR (Results 1 – 25 of 70) sorted by relevance

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/ThreadX-v6.3.0/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports/cortex_a75/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports/cortex_a76/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports/cortex_a76/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports/cortex_a76ae/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports/cortex_a77/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports/cortex_a77/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports/cortex_a76ae/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.3.0/ports/cortex_a65/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()

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