Home
last modified time | relevance | path

Searched refs:GICD_CTLR (Results 1 – 25 of 138) sorted by relevance

123456

/ThreadX-v6.3.0/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports/cortex_a75/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports/cortex_a76/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports/cortex_a76/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports/cortex_a76ae/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports/cortex_a77/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports/cortex_a77/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports/cortex_a76ae/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()
/ThreadX-v6.3.0/ports/cortex_a65/ac6/example_build/sample_threadx/
DGICv3_gicd.c15 volatile uint32_t GICD_CTLR; // +0x0000 member
77 gicd.GICD_CTLR = flags; in ConfigGICD()
82 gicd.GICD_CTLR |= flags; in EnableGICD()
87 gicd.GICD_CTLR &= ~flags; in DisableGICD()
97 while ((gicd.GICD_CTLR & tmask) != tval) in SyncAREinGICD()
101 gicd.GICD_CTLR = flags; in SyncAREinGICD()

123456