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/ThreadX-v6.3.0/ports/cortex_a5x/ac6/example_build/sample_threadx/
Dgic400_gic.c38 volatile unsigned int GICC_CTLR; // +0x000 - RW - CPU Interface Control Register member
322 tmp = gic_cpu->GICC_CTLR; in enableCPUInterface()
324 gic_cpu->GICC_CTLR = tmp; in enableCPUInterface()
334 tmp = gic_cpu->GICC_CTLR; in enableNonSecureCPUInterface()
336 gic_cpu->GICC_CTLR = tmp; in enableNonSecureCPUInterface()
344 tmp = gic_cpu->GICC_CTLR; in disableCPUInterface()
346 gic_cpu->GICC_CTLR = tmp; in disableCPUInterface()
354 tmp = gic_cpu->GICC_CTLR; in enableSecureFIQs()
356 gic_cpu->GICC_CTLR = tmp; in enableSecureFIQs()
364 tmp = gic_cpu->GICC_CTLR; in disableSecureFIQs()
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/ThreadX-v6.3.0/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports/cortex_a75/gnu/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports/cortex_a76/ac6/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports/cortex_a76/gnu/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports/cortex_a76ae/gnu/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports/cortex_a77/ac6/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports/cortex_a77/gnu/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports/cortex_a76ae/ac6/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro
/ThreadX-v6.3.0/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/
DPPM_AEM.h50 #define GICC_CTLR 0x0000 macro

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