| /ThreadX-v6.3.0/ports/cortex_a9/gnu/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports_arch/ARMv7-A/threadx/common/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a8/ac6/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a8/gnu/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a9/ac6/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a12/ac6/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a12/gnu/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a15/ac6/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a15/gnu/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a7/gnu/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a7/ac6/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a5/ac6/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a5/gnu/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a17/ac6/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a17/gnu/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports_module/cortex_a7/gnu/module_manager/src/ |
| D | tx_thread_fiq_nesting_start.s | 23 FIQ_DISABLE = 0x40 // FIQ disable bit define
98 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a9/iar/src/ |
| D | tx_thread_fiq_nesting_start.s | 34 FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit label
95 BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a5/iar/src/ |
| D | tx_thread_fiq_nesting_start.s | 34 FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit label
95 BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a8/iar/src/ |
| D | tx_thread_fiq_nesting_start.s | 34 FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit label
95 BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/arm9/iar/src/ |
| D | tx_thread_fiq_nesting_start.s | 34 FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit label
95 BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/arm11/iar/src/ |
| D | tx_thread_fiq_nesting_start.s | 34 FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit label
95 BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a7/iar/src/ |
| D | tx_thread_fiq_nesting_start.s | 34 FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit label
95 BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports_module/cortex_a7/iar/module_manager/src/ |
| D | tx_thread_fiq_nesting_start.s | 23 FIQ_DISABLE EQU 0x40 ; FIQ disable bit define
86 BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/arm9/gnu/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 @ FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/arm11/gnu/src/ |
| D | tx_thread_fiq_nesting_start.S | 26 FIQ_DISABLE = 0x40 @ FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR
|
