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/ThreadX-v6.3.0/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/
Dtx_zynqmp_low_level.c232 #define DDR_0_SIZE 0x80000000u in mmu_tbl_init() macro
233 #define DDR_0_REG (DDR_0_SIZE/0x200000) in mmu_tbl_init()