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Searched refs:CPSR_MASK (Results 1 – 25 of 62) sorted by relevance

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/ThreadX-v6.3.0/ports_module/cortex_r4/ac6/module_manager/src/
Dtx_thread_stack_build.S37 #define CPSR_MASK 0xDF // Mask initial CPSR, IRQ & FIQ ints enabled macro
39 #define CPSR_MASK 0x9F // Mask initial CPSR, IRQ ints enabled macro
149 BIC r3, r3, #CPSR_MASK // Mask mode bits of CPSR
Dtxm_module_manager_thread_stack_build.S27 #define CPSR_MASK 0xBF // Mask initial CPSR, IRQ ints enabled macro
132 BIC r3, r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports_module/cortex_a7/gnu/module_manager/src/
Dtx_thread_stack_build.s36 CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabl… define
38 CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled define
132 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
Dtxm_module_manager_thread_stack_build.s34 #define CPSR_MASK 0xDF // Mask initial CPSR, IRQ & FIQ ints enabled macro
36 #define CPSR_MASK 0x9F // Mask initial CPSR, IRQ ints enabled macro
148 BIC r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_r4/ac6/src/
Dtx_thread_stack_build.S35 #define CPSR_MASK 0xDF // Mask initial CPSR, IRQ & FIQ ints enabled macro
37 #define CPSR_MASK 0x9F // Mask initial CPSR, IRQ ints enabled macro
150 BIC r3, r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_a9/gnu/src/
Dtx_thread_stack_build.S30 CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled define
32 CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled define
159 BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports_arch/ARMv7-A/threadx/common/src/
Dtx_thread_stack_build.S30 CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled define
32 CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled define
159 BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_a8/ac6/src/
Dtx_thread_stack_build.S30 CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled define
32 CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled define
159 BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_a8/gnu/src/
Dtx_thread_stack_build.S30 CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled define
32 CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled define
159 BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_a9/ac6/src/
Dtx_thread_stack_build.S30 CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled define
32 CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled define
159 BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_a12/ac6/src/
Dtx_thread_stack_build.S30 CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled define
32 CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled define
159 BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_a12/gnu/src/
Dtx_thread_stack_build.S30 CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled define
32 CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled define
159 BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_a15/ac6/src/
Dtx_thread_stack_build.S30 CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled define
32 CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled define
159 BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_a15/gnu/src/
Dtx_thread_stack_build.S30 CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled define
32 CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled define
159 BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_a7/ac6/src/
Dtx_thread_stack_build.S30 CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled define
32 CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled define
159 BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_a7/gnu/src/
Dtx_thread_stack_build.S30 CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled define
32 CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled define
159 BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_a5/ac6/src/
Dtx_thread_stack_build.S30 CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled define
32 CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled define
159 BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_a5/gnu/src/
Dtx_thread_stack_build.S30 CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled define
32 CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled define
159 BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_a17/ac6/src/
Dtx_thread_stack_build.S30 CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled define
32 CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled define
159 BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_a17/gnu/src/
Dtx_thread_stack_build.S30 CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled define
32 CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled define
159 BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports_smp/cortex_r8_smp/ac5/src/
Dtx_thread_stack_build.s25 CPSR_MASK EQU 0xDF // Mask initial CPSR, IRQ & FIQ ints enabled define
27 CPSR_MASK EQU 0x9F // Mask initial CPSR, IRQ ints enabled define
132 BIC r3, r3, #CPSR_MASK // Mask mode bits of CPSR
/ThreadX-v6.3.0/ports_module/cortex_a7/iar/module_manager/src/
Dtxm_module_manager_thread_stack_build.s28 CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled define
30 CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled define
/ThreadX-v6.3.0/ports_module/cortex_a7/ac5/module_manager/src/
Dtxm_module_manager_thread_stack_build.s37 CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled define
39 CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled define
/ThreadX-v6.3.0/ports/cortex_a9/iar/src/
Dtx_thread_stack_build.s35 CPSR_MASK DEFINE 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled label
37 CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled label
142 BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR
/ThreadX-v6.3.0/ports/cortex_a8/iar/src/
Dtx_thread_stack_build.s35 CPSR_MASK DEFINE 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled label
37 CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled label
142 BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR

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