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/ThreadX-v6.2.1/ports/xtensa/xcc/src/
Dxtensa_intr.c59 xt_exc_handler xt_set_exception_handler(uint32_t n, xt_exc_handler f) in xt_set_exception_handler() argument
63 if (n >= XCHAL_EXCCAUSE_NUM) { in xt_set_exception_handler()
67 old = _xt_exception_table[n]; in xt_set_exception_handler()
70 _xt_exception_table[n] = f; in xt_set_exception_handler()
73 _xt_exception_table[n] = &xt_unhandled_exception; in xt_set_exception_handler()
119 xt_handler xt_set_interrupt_handler(uint32_t n, xt_handler f, void * arg) in xt_set_interrupt_handler() argument
124 if (n >= XCHAL_NUM_INTERRUPTS) { in xt_set_interrupt_handler()
129 if (Xthal_intlevel[n] > XCHAL_EXCM_LEVEL) { in xt_set_interrupt_handler()
135 entry = _xt_interrupt_table + n + 1; in xt_set_interrupt_handler()
137 entry = _xt_interrupt_table + n; in xt_set_interrupt_handler()
[all …]
/ThreadX-v6.2.1/ports/cortex_m23/ac6/example_build/demo_secure_zone/
Dtz_context.c57 uint32_t n; in TZ_InitContextSystem_S() local
63 for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { in TZ_InitContextSystem_S()
64 ProcessStackInfo[n].sp = 0U; in TZ_InitContextSystem_S()
65 ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; in TZ_InitContextSystem_S()
66 ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; in TZ_InitContextSystem_S()
67 *((uint32_t *)ProcessStackMemory[n]) = n + 1U; in TZ_InitContextSystem_S()
69 *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; in TZ_InitContextSystem_S()
/ThreadX-v6.2.1/ports/cortex_m55/ac6/example_build/demo_secure_zone/
Dtz_context.c57 uint32_t n; in TZ_InitContextSystem_S() local
63 for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { in TZ_InitContextSystem_S()
64 ProcessStackInfo[n].sp = 0U; in TZ_InitContextSystem_S()
65 ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; in TZ_InitContextSystem_S()
66 ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; in TZ_InitContextSystem_S()
67 *((uint32_t *)ProcessStackMemory[n]) = n + 1U; in TZ_InitContextSystem_S()
69 *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; in TZ_InitContextSystem_S()
/ThreadX-v6.2.1/ports/cortex_m33/ac6/example_build/demo_secure_zone/
Dtz_context.c57 uint32_t n; in TZ_InitContextSystem_S() local
63 for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { in TZ_InitContextSystem_S()
64 ProcessStackInfo[n].sp = 0U; in TZ_InitContextSystem_S()
65 ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; in TZ_InitContextSystem_S()
66 ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; in TZ_InitContextSystem_S()
67 *((uint32_t *)ProcessStackMemory[n]) = n + 1U; in TZ_InitContextSystem_S()
69 *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; in TZ_InitContextSystem_S()
/ThreadX-v6.2.1/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/
Dtz_context.c57 uint32_t n; in TZ_InitContextSystem_S() local
63 for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { in TZ_InitContextSystem_S()
64 ProcessStackInfo[n].sp = 0U; in TZ_InitContextSystem_S()
65 ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; in TZ_InitContextSystem_S()
66 ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; in TZ_InitContextSystem_S()
67 *((uint32_t *)ProcessStackMemory[n]) = n + 1U; in TZ_InitContextSystem_S()
69 *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; in TZ_InitContextSystem_S()
/ThreadX-v6.2.1/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/
Darc.h56 int n; in __ffs() local
61 : "=r"(n) in __ffs()
65 return n; in __ffs()
/ThreadX-v6.2.1/ports/risc-v32/iar/example_build/config/debugger/
Dtimer.mac21 __message "execUserSetup() called\n";
29 __message "execUserExit() called\n";
49 __message "ERROR: could not set immediate breakpoint.\n" ;
56 __message "Entered TIMER interrupt: ", _counter, "\n";
/ThreadX-v6.2.1/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/
Dpartition_ARMCM23.h721 #define SAU_INIT_REGION(n) \ argument
722 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
723 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
724 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
725 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/ThreadX-v6.2.1/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/
Dpartition_ARMCM23.h721 #define SAU_INIT_REGION(n) \ argument
722 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
723 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
724 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
725 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/ThreadX-v6.2.1/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/
Dpartition_ARMCM23.h721 #define SAU_INIT_REGION(n) \ argument
722 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
723 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
724 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
725 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/ThreadX-v6.2.1/ports/xtensa/xcc/inc/
Dxtensa_api.h60 extern xt_exc_handler xt_set_exception_handler(uint32_t n, xt_exc_handler f);
72 extern xt_handler xt_set_interrupt_handler(uint32_t n, xt_handler f, void * arg);
Dxtensa_context.h55 #define ALIGNUP(n, val) (((val) + (n)-1) & -(n)) argument
67 #define XSTRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n) argument
74 #define XSTRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n]; argument
/ThreadX-v6.2.1/ports/cortex_m55/ac6/example_build/
DCS300_ac6.sct14 1 0x0000_0000 0x000F_FFFF 1MB Code ITCM 4 NS n/a
15 2 0x0010_0000 0x002F_FFFF 2MB Code SRAM (only 2MB) 5 NS n/a
16 4 0x1000_0000 0x100F_FFFF 1MB Code ITCM 1 S n/a
18 7 0x2000_0000 0x203F_FFFF 4MB SRAM DTCM (4 x 1MB) 11 NS n/a
19 11 0x3000_0000 0x303F_FFFF 4MB SRAM DTCM (4 x 1MB) 7 S n/a
DCS300_ac6_s.sct14 1 0x0000_0000 0x000F_FFFF 1MB Code ITCM 4 NS n/a
15 2 0x0010_0000 0x002F_FFFF 2MB Code SRAM (only 2MB) 5 NS n/a
16 4 0x1000_0000 0x100F_FFFF 1MB Code ITCM 1 S n/a
18 7 0x2000_0000 0x203F_FFFF 4MB SRAM DTCM (4 x 1MB) 11 NS n/a
19 11 0x3000_0000 0x303F_FFFF 4MB SRAM DTCM (4 x 1MB) 7 S n/a
/ThreadX-v6.2.1/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/
Dpartition_ARMCM33.h1110 #define SAU_INIT_REGION(n) \ argument
1111 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
1112 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
1113 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
1114 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/ThreadX-v6.2.1/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/
Dpartition_ARMCM33.h1110 #define SAU_INIT_REGION(n) \ argument
1111 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
1112 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
1113 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
1114 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/ThreadX-v6.2.1/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/
Dpartition_ARMCM33.h1110 #define SAU_INIT_REGION(n) \ argument
1111 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
1112 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
1113 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
1114 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/ThreadX-v6.2.1/ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/
Dpartition_CS300.h1110 #define SAU_INIT_REGION(n) \ argument
1111 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
1112 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
1113 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
1114 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/ThreadX-v6.2.1/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/
Dpartition_ARMCM33.h1110 #define SAU_INIT_REGION(n) \ argument
1111 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
1112 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
1113 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
1114 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/ThreadX-v6.2.1/common_smp/inc/
Dtx_api.h1310 #define tx_block_pool_create(p,n,b,s,l) _txr_block_pool_create((p),(n),(b),(s),(l),(siz… argument
1319 #define tx_byte_pool_create(p,n,s,l) _txr_byte_pool_create((p),(n),(s),(l),(sizeof(T… argument
1327 #define tx_event_flags_create(g,n) _txr_event_flags_create((g),(n),(sizeof(TX_EVEN… argument
1347 #define tx_mutex_create(m,n,i) _txr_mutex_create((m),(n),(i),(sizeof(TX_MUTEX)… argument
1356 #define tx_queue_create(q,n,m,s,l) _txr_queue_create((q),(n),(m),(s),(l),(sizeof(T… argument
1369 #define tx_semaphore_create(s,n,i) _txr_semaphore_create((s),(n),(i),(sizeof(TX_SE… argument
1379 #define tx_thread_create(t,n,e,i,s,l,p,r,c,a) _txr_thread_create((t),(n),(e),(i),(s),(l),(p),… argument
1408 #define tx_timer_create(t,n,e,i,c,r,a) _txr_timer_create((t),(n),(e),(i),(c),(r),(a),(… argument
1427 #define tx_block_pool_create(p,n,b,s,l) _txe_block_pool_create((p),(n),(b),(s),(l),(siz… argument
1436 #define tx_byte_pool_create(p,n,s,l) _txe_byte_pool_create((p),(n),(s),(l),(sizeof(T… argument
[all …]
Dtx_trace.h61 #define TX_TRACE_OBJECT_REGISTER(t,p,n,a,b) argument
463 …e TX_TRACE_OBJECT_REGISTER(t,p,n,a,b) _tx_trace_object_register((UCHAR) (t), (… argument
/ThreadX-v6.2.1/common/inc/
Dtx_api.h1224 #define tx_block_pool_create(p,n,b,s,l) _txr_block_pool_create((p),(n),(b),(s),(l),(siz… argument
1233 #define tx_byte_pool_create(p,n,s,l) _txr_byte_pool_create((p),(n),(s),(l),(sizeof(T… argument
1241 #define tx_event_flags_create(g,n) _txr_event_flags_create((g),(n),(sizeof(TX_EVEN… argument
1262 #define tx_mutex_create(m,n,i) _txr_mutex_create((m),(n),(i),(sizeof(TX_MUTEX)… argument
1271 #define tx_queue_create(q,n,m,s,l) _txr_queue_create((q),(n),(m),(s),(l),(sizeof(T… argument
1284 #define tx_semaphore_create(s,n,i) _txr_semaphore_create((s),(n),(i),(sizeof(TX_SE… argument
1294 #define tx_thread_create(t,n,e,i,s,l,p,r,c,a) _txr_thread_create((t),(n),(e),(i),(s),(l),(p),… argument
1317 #define tx_timer_create(t,n,e,i,c,r,a) _txr_timer_create((t),(n),(e),(i),(c),(r),(a),(… argument
1336 #define tx_block_pool_create(p,n,b,s,l) _txe_block_pool_create((p),(n),(b),(s),(l),(siz… argument
1345 #define tx_byte_pool_create(p,n,s,l) _txe_byte_pool_create((p),(n),(s),(l),(sizeof(T… argument
[all …]
Dtx_trace.h61 #define TX_TRACE_OBJECT_REGISTER(t,p,n,a,b) argument
463 …e TX_TRACE_OBJECT_REGISTER(t,p,n,a,b) _tx_trace_object_register((UCHAR) (t), (… argument
/ThreadX-v6.2.1/
DLICENSE.txt216 n’accorde aucune autre garantie expresse. Vous pouvez bénéficier de droits
226 les dommages spéciaux, indirects ou accessoires et pertes de bénéfices.
234 de responsabilité stricte, de négligence ou d’une autre faute dans la limite
238 l’éventualité d’un tel dommage. Si votre pays n’autorise pas l’exclusion ou la
/ThreadX-v6.2.1/ports_smp/mips32_interaptiv_smp/green/example_build/
Dinit_vpe1.mip195 // For VPE1..n

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