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Searched refs:mmu_tbl0 (Results 1 – 2 of 2) sorted by relevance

/ThreadX-v6.2.1/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/
Dtx_zynqmp_low_level.c139 static uint64_t mmu_tbl0[2]; variable
177 mmu_tbl0[0] = ((uint64_t) mmu_tbl1) + 0x3; in mmu_tbl_init()
179 mmu_tbl0[1] = ((uint64_t) mmu_tbl1) + 0x1000 + 0x3; in mmu_tbl_init()
281 __MSR(__TTBR0_EL3, (uint64_t) mmu_tbl0); in tx_caches_enable()
/ThreadX-v6.2.1/ports_smp/cortex_a5x_smp/green/example_build/tgt/
Dstandalone_ram.ld45 .mmu_tbl0 ALIGN(4096) : > .