| /ThreadX-v6.2.1/ports_module/cortex_a7/iar/module_manager/src/ |
| D | tx_thread_interrupt_control.s | 25 INT_MASK EQU 0xC0 ; Interrupt bit mask
27 INT_MASK EQU 0x80 ; Interrupt bit mask
86 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/arm9/iar/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK DEFINE 0xC0 ; Interrupt bit mask
35 INT_MASK DEFINE 0x80 ; Interrupt bit mask
93 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/cortex_a9/iar/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK DEFINE 0xC0 ; Interrupt bit mask
35 INT_MASK DEFINE 0x80 ; Interrupt bit mask
93 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports_smp/cortex_a5_smp/gnu/src/ |
| D | tx_thread_interrupt_control.S | 33 INT_MASK = 0xC0 @ Interrupt bit mask
35 INT_MASK = 0x80 @ Interrupt bit mask
95 AND r0, r3, #INT_MASK @ Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/cortex_a5/iar/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK DEFINE 0xC0 ; Interrupt bit mask
35 INT_MASK DEFINE 0x80 ; Interrupt bit mask
93 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/arm11/iar/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK DEFINE 0xC0 ; Interrupt bit mask
35 INT_MASK DEFINE 0x80 ; Interrupt bit mask
93 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/cortex_a7/iar/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK DEFINE 0xC0 ; Interrupt bit mask
35 INT_MASK DEFINE 0x80 ; Interrupt bit mask
93 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports_smp/cortex_a7_smp/gnu/src/ |
| D | tx_thread_interrupt_control.S | 33 INT_MASK = 0xC0 @ Interrupt bit mask
35 INT_MASK = 0x80 @ Interrupt bit mask
95 AND r0, r3, #INT_MASK @ Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports_smp/cortex_a9_smp/gnu/src/ |
| D | tx_thread_interrupt_control.S | 33 INT_MASK = 0xC0 @ Interrupt bit mask
35 INT_MASK = 0x80 @ Interrupt bit mask
95 AND r0, r3, #INT_MASK @ Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/cortex_a8/iar/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK DEFINE 0xC0 ; Interrupt bit mask
35 INT_MASK DEFINE 0x80 ; Interrupt bit mask
93 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/linux/gnu/src/ |
| D | tx_initialize_low_level.c | 229 cpu_set_t mask; in _tx_initialize_low_level() local
231 sched_getaffinity(getpid(), sizeof(mask), &mask); in _tx_initialize_low_level()
232 if (CPU_COUNT(&mask) > 1) in _tx_initialize_low_level()
238 CPU_ZERO(&mask); in _tx_initialize_low_level()
239 CPU_SET(rand() % get_nprocs(), &mask); in _tx_initialize_low_level()
240 if (sched_setaffinity(getpid(), sizeof(mask), &mask) != 0) in _tx_initialize_low_level()
|
| /ThreadX-v6.2.1/ports/cortex_a8/ac5/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK EQU 0xC0 ; Interrupt bit mask
35 INT_MASK EQU 0x80 ; Interrupt bit mask
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/cortex_r4/ac5/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK EQU 0xC0 ; Interrupt bit mask
35 INT_MASK EQU 0x80 ; Interrupt bit mask
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/cortex_r5/ac5/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK EQU 0xC0 ; Interrupt bit mask
35 INT_MASK EQU 0x80 ; Interrupt bit mask
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports_smp/cortex_a5_smp/ac5/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK EQU 0xC0 ; Interrupt bit mask
35 INT_MASK EQU 0x80 ; Interrupt bit mask
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/cortex_a5/ac5/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK EQU 0xC0 ; Interrupt bit mask
35 INT_MASK EQU 0x80 ; Interrupt bit mask
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/arm11/ac5/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK EQU 0xC0 ; Interrupt bit mask
35 INT_MASK EQU 0x80 ; Interrupt bit mask
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/arm9/ac5/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK EQU 0xC0 ; Interrupt bit mask
35 INT_MASK EQU 0x80 ; Interrupt bit mask
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/cortex_a7/ac5/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK EQU 0xC0 ; Interrupt bit mask
35 INT_MASK EQU 0x80 ; Interrupt bit mask
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports_smp/cortex_a9_smp/ac5/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK EQU 0xC0 ; Interrupt bit mask
35 INT_MASK EQU 0x80 ; Interrupt bit mask
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports_module/cortex_a7/ac5/module_manager/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK EQU 0xC0 ; Interrupt bit mask
35 INT_MASK EQU 0x80 ; Interrupt bit mask
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/cortex_a9/ac5/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK EQU 0xC0 ; Interrupt bit mask
35 INT_MASK EQU 0x80 ; Interrupt bit mask
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports_smp/cortex_a7_smp/ac5/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK EQU 0xC0 ; Interrupt bit mask
35 INT_MASK EQU 0x80 ; Interrupt bit mask
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/cortex_r5/iar/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK DEFINE 0x80 ; Interrupt bit mask
90 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
| /ThreadX-v6.2.1/ports/cortex_r4/iar/src/ |
| D | tx_thread_interrupt_control.s | 33 INT_MASK DEFINE 0x80 ; Interrupt bit mask
90 AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
