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Searched refs:THUMB_MASK (Results 1 – 25 of 61) sorted by relevance

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/ThreadX-v6.2.1/ports_module/cortex_r4/ac6/module_manager/src/
Dtxm_module_manager_thread_stack_build.S24 #define THUMB_MASK 0x20 // THUMB bit macro
134 ORRNE r3, r3, #THUMB_MASK // Set T bit if set
Dtx_thread_context_restore.S38 #define THUMB_MASK 0x20 // Thumb bit mask macro
247 BIC r1, r1, #THUMB_MASK // Clear thumb bit
Dtx_thread_schedule.S42 #define THUMB_MASK 0x20 // Thumb bit (5) of CPSR/SPSR. macro
124 TST r0, #THUMB_MASK // Occurred in Thumb state?
417 ORRNE r2, r2, #THUMB_MASK // If so, set Thumb bit
418 BICEQ r2, r2, #THUMB_MASK // If not, clear Thumb bit
/ThreadX-v6.2.1/ports_module/cortex_a7/gnu/module_manager/src/
Dtxm_module_manager_thread_stack_build.s24 #define THUMB_MASK 0x20 // THUMB bit macro
137 ORRNE r3, r3, #THUMB_MASK // Set T bit if set
/ThreadX-v6.2.1/ports_module/cortex_a7/ac5/module_manager/src/
Dtx_thread_stack_build.s41 THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR define
147 BIC r3, r3, #THUMB_MASK ; Clear Thumb bit by default
150 ORREQ r3, r3, #THUMB_MASK ; Yes, set the Thumb bit
Dtxm_module_manager_thread_stack_build.s33 THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR define
/ThreadX-v6.2.1/ports_module/cortex_a7/iar/module_manager/src/
Dtx_thread_stack_build.s31 THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR define
137 BIC r3, r3, #THUMB_MASK ; Clear Thumb bit by default
140 ORREQ r3, r3, #THUMB_MASK ; Yes, set the Thumb bit
Dtxm_module_manager_thread_stack_build.s24 THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR define
/ThreadX-v6.2.1/ports_module/cortex_r4/iar/module_manager/src/
Dtxm_module_manager_thread_stack_build.s24 THUMB_MASK DEFINE 0x20 ; THUMB bit label
Dtx_thread_context_restore.s29 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
224 BIC r1, r1, #THUMB_MASK ; Clear thumb bit - slarson
/ThreadX-v6.2.1/ports/cortex_r5/iar/src/
Dtx_thread_context_restore.s38 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
200 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
/ThreadX-v6.2.1/ports/cortex_r4/iar/src/
Dtx_thread_context_restore.s38 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
200 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
/ThreadX-v6.2.1/ports/arm11/ac5/src/
Dtx_thread_context_restore.s42 THUMB_MASK EQU 0x20 ; Thumb bit mask define
199 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
/ThreadX-v6.2.1/ports/arm9/iar/src/
Dtx_thread_context_restore.s41 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
196 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
/ThreadX-v6.2.1/ports_module/cortex_r4/ac6/example_build/sample_threadx/
Dtx_initialize_low_level.S36 #define THUMB_MASK 0x20 // Thumb bit (5) of CPSR/SPSR macro
445 BIC r0, r0, #THUMB_MASK // Clear THUMB mode
/ThreadX-v6.2.1/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/
Dtx_initialize_low_level.S36 #define THUMB_MASK 0x20 // Thumb bit (5) of CPSR/SPSR macro
445 BIC r0, r0, #THUMB_MASK // Clear THUMB mode
/ThreadX-v6.2.1/ports/arm11/iar/src/
Dtx_thread_context_restore.s42 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
198 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
/ThreadX-v6.2.1/ports/arm9/ac5/src/
Dtx_thread_context_restore.s42 THUMB_MASK EQU 0x20 ; Thumb bit mask define
199 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
/ThreadX-v6.2.1/ports_module/cortex_a7/gnu/example_build/
Dtx_initialize_low_level.s32 THUMB_MASK = 0x20 // THUMB mode bit define
393 BIC r0, r0, #THUMB_MASK // Clear THUMB mode
/ThreadX-v6.2.1/ports/cortex_a5/iar/src/
Dtx_thread_context_restore.s41 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
215 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
/ThreadX-v6.2.1/ports/arm11/gnu/src/
Dtx_thread_fiq_context_restore.S30 THUMB_MASK = 0x20 @ Thumb bit mask define
203 BIC r4, r4, #THUMB_MASK @ Clear the Thumb bit of CPSR
/ThreadX-v6.2.1/ports/cortex_a7/iar/src/
Dtx_thread_context_restore.s41 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
213 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
/ThreadX-v6.2.1/ports/arm9/gnu/src/
Dtx_thread_fiq_context_restore.S30 THUMB_MASK = 0x20 @ Thumb bit mask define
203 BIC r4, r4, #THUMB_MASK @ Clear the Thumb bit of CPSR
/ThreadX-v6.2.1/ports/cortex_a9/iar/src/
Dtx_thread_context_restore.s41 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
213 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR
/ThreadX-v6.2.1/ports/cortex_a8/iar/src/
Dtx_thread_context_restore.s41 THUMB_MASK DEFINE 0x20 ; Thumb bit mask label
213 BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR

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