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/ThreadX-v6.2.1/ports_smp/cortex_r8_smp/ac5/src/
Dtx_thread_vectored_context_save.s25 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
82 IF :DEF:TX_ENABLE_FIQ_SUPPORT
109 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
118 IF {INTER} = {TRUE}
150 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
159 IF {INTER} = {TRUE}
178 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
188 IF {INTER} = {TRUE}
Dtx_thread_schedule.s26 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
80 IF :DEF:TX_ENABLE_FIQ_SUPPORT
97 IF :DEF:TX_ENABLE_FIQ_SUPPORT
156 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
172 IF {TARGET_FPU_VFP} = {TRUE}
184 IF {TARGET_FPU_VFP} = {TRUE}
201 IF {TARGET_FPU_VFP} = {TRUE}
205 IF :DEF:TX_ENABLE_FIQ_SUPPORT
227 IF :DEF:TX_ENABLE_FIQ_SUPPORT
Dtx_thread_context_save.s26 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
92 IF :DEF:TX_ENABLE_FIQ_SUPPORT
117 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
152 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
176 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
Dtx_thread_system_return.s28 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
92 IF {TARGET_FPU_VFP} = {TRUE}
107 IF :DEF:TX_ENABLE_FIQ_SUPPORT
113 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
170 IF :DEF:TX_MPCORE_DEBUG_ENABLE
Dtx_thread_interrupt_disable.s72 IF :DEF:TX_ENABLE_FIQ_SUPPORT
78 IF {INTER} = {TRUE}
/ThreadX-v6.2.1/ports/arm11/ac5/src/
Dtx_thread_vectored_context_save.s33 IF :DEF:TX_ENABLE_FIQ_SUPPORT
42 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
100 IF :DEF:TX_ENABLE_FIQ_SUPPORT
121 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
130 IF {INTER} = {TRUE}
161 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
170 IF {INTER} = {TRUE}
189 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
199 IF {INTER} = {TRUE}
/ThreadX-v6.2.1/ports/arm9/ac5/src/
Dtx_thread_vectored_context_save.s33 IF :DEF:TX_ENABLE_FIQ_SUPPORT
42 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
100 IF :DEF:TX_ENABLE_FIQ_SUPPORT
121 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
130 IF {INTER} = {TRUE}
161 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
170 IF {INTER} = {TRUE}
189 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
199 IF {INTER} = {TRUE}
/ThreadX-v6.2.1/ports/cortex_a7/ac5/src/
Dtx_thread_vectored_context_save.s35 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
93 IF :DEF:TX_ENABLE_FIQ_SUPPORT
112 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
121 IF {INTER} = {TRUE}
152 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
161 IF {INTER} = {TRUE}
180 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
190 IF {INTER} = {TRUE}
/ThreadX-v6.2.1/ports/cortex_r4/ac5/src/
Dtx_thread_vectored_context_save.s35 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
93 IF :DEF:TX_ENABLE_FIQ_SUPPORT
112 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
121 IF {INTER} = {TRUE}
152 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
161 IF {INTER} = {TRUE}
180 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
190 IF {INTER} = {TRUE}
Dtx_thread_schedule.s37 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
92 IF :DEF:TX_ENABLE_FIQ_SUPPORT
115 IF :DEF:TX_ENABLE_FIQ_SUPPORT
143 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
162 IF {TARGET_FPU_VFP} = {TRUE}
175 IF {TARGET_FPU_VFP} = {TRUE}
186 IF {INTER} = {TRUE}
195 IF {TARGET_FPU_VFP} = {TRUE}
199 IF :DEF:TX_ENABLE_FIQ_SUPPORT
217 IF :DEF:TX_ENABLE_FIQ_SUPPORT
/ThreadX-v6.2.1/ports/cortex_r5/ac5/src/
Dtx_thread_vectored_context_save.s35 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
93 IF :DEF:TX_ENABLE_FIQ_SUPPORT
112 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
121 IF {INTER} = {TRUE}
152 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
161 IF {INTER} = {TRUE}
180 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
190 IF {INTER} = {TRUE}
Dtx_thread_schedule.s37 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
92 IF :DEF:TX_ENABLE_FIQ_SUPPORT
115 IF :DEF:TX_ENABLE_FIQ_SUPPORT
146 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
160 IF {TARGET_FPU_VFP} = {TRUE}
172 IF {TARGET_FPU_VFP} = {TRUE}
185 IF {INTER} = {TRUE}
194 IF {TARGET_FPU_VFP} = {TRUE}
198 IF :DEF:TX_ENABLE_FIQ_SUPPORT
216 IF :DEF:TX_ENABLE_FIQ_SUPPORT
/ThreadX-v6.2.1/ports/cortex_a5/ac5/src/
Dtx_thread_vectored_context_save.s35 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
93 IF :DEF:TX_ENABLE_FIQ_SUPPORT
112 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
121 IF {INTER} = {TRUE}
152 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
161 IF {INTER} = {TRUE}
180 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
190 IF {INTER} = {TRUE}
/ThreadX-v6.2.1/ports/cortex_a8/ac5/src/
Dtx_thread_vectored_context_save.s35 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
93 IF :DEF:TX_ENABLE_FIQ_SUPPORT
112 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
121 IF {INTER} = {TRUE}
152 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
161 IF {INTER} = {TRUE}
180 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
190 IF {INTER} = {TRUE}
/ThreadX-v6.2.1/ports_module/cortex_a7/ac5/module_manager/src/
Dtx_thread_vectored_context_save.s35 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
93 IF :DEF:TX_ENABLE_FIQ_SUPPORT
112 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
121 IF {INTER} = {TRUE}
152 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
161 IF {INTER} = {TRUE}
180 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
190 IF {INTER} = {TRUE}
/ThreadX-v6.2.1/ports/cortex_a9/ac5/src/
Dtx_thread_vectored_context_save.s35 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
93 IF :DEF:TX_ENABLE_FIQ_SUPPORT
112 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
121 IF {INTER} = {TRUE}
152 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
161 IF {INTER} = {TRUE}
180 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
190 IF {INTER} = {TRUE}
/ThreadX-v6.2.1/ports_smp/cortex_a7_smp/ac5/src/
Dtx_thread_vectored_context_save.s35 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
93 IF :DEF:TX_ENABLE_FIQ_SUPPORT
120 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
129 IF {INTER} = {TRUE}
161 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
170 IF {INTER} = {TRUE}
189 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
199 IF {INTER} = {TRUE}
/ThreadX-v6.2.1/ports_smp/cortex_a5_smp/ac5/src/
Dtx_thread_vectored_context_save.s35 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
93 IF :DEF:TX_ENABLE_FIQ_SUPPORT
120 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
129 IF {INTER} = {TRUE}
161 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
170 IF {INTER} = {TRUE}
189 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
199 IF {INTER} = {TRUE}
/ThreadX-v6.2.1/ports_smp/cortex_a9_smp/ac5/src/
Dtx_thread_vectored_context_save.s35 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
93 IF :DEF:TX_ENABLE_FIQ_SUPPORT
120 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
129 IF {INTER} = {TRUE}
161 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
170 IF {INTER} = {TRUE}
189 IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
199 IF {INTER} = {TRUE}
/ThreadX-v6.2.1/ports/cortex_a5/ac5/example_build/
Dtx_initialize_low_level.s35 IF :DEF:TX_ENABLE_FIQ_SUPPORT
58 IF :DEF:TX_ENABLE_FIQ_SUPPORT
62 IF :DEF:TX_ENABLE_IRQ_NESTING
66 IF :DEF:TX_ENABLE_FIQ_NESTING
150 IF :DEF:TX_ENABLE_IRQ_NESTING
196 IF {INTER} = {TRUE}
215 IF :DEF:TX_ENABLE_IRQ_NESTING
226 IF {INTER} = {TRUE}
281 IF :DEF:TX_ENABLE_IRQ_NESTING
291 IF :DEF:TX_ENABLE_IRQ_NESTING
[all …]
/ThreadX-v6.2.1/ports/cortex_a8/ac5/example_build/
Dtx_initialize_low_level.s35 IF :DEF:TX_ENABLE_FIQ_SUPPORT
58 IF :DEF:TX_ENABLE_FIQ_SUPPORT
62 IF :DEF:TX_ENABLE_IRQ_NESTING
66 IF :DEF:TX_ENABLE_FIQ_NESTING
150 IF :DEF:TX_ENABLE_IRQ_NESTING
196 IF {INTER} = {TRUE}
215 IF :DEF:TX_ENABLE_IRQ_NESTING
226 IF {INTER} = {TRUE}
281 IF :DEF:TX_ENABLE_IRQ_NESTING
291 IF :DEF:TX_ENABLE_IRQ_NESTING
[all …]
/ThreadX-v6.2.1/ports/cortex_r4/ac5/example_build/
Dtx_initialize_low_level.s35 IF :DEF:TX_ENABLE_FIQ_SUPPORT
58 IF :DEF:TX_ENABLE_FIQ_SUPPORT
62 IF :DEF:TX_ENABLE_IRQ_NESTING
66 IF :DEF:TX_ENABLE_FIQ_NESTING
150 IF :DEF:TX_ENABLE_IRQ_NESTING
196 IF {INTER} = {TRUE}
215 IF :DEF:TX_ENABLE_IRQ_NESTING
226 IF {INTER} = {TRUE}
281 IF :DEF:TX_ENABLE_IRQ_NESTING
291 IF :DEF:TX_ENABLE_IRQ_NESTING
[all …]
/ThreadX-v6.2.1/ports/cortex_r5/ac5/example_build/
Dtx_initialize_low_level.s35 IF :DEF:TX_ENABLE_FIQ_SUPPORT
58 IF :DEF:TX_ENABLE_FIQ_SUPPORT
62 IF :DEF:TX_ENABLE_IRQ_NESTING
66 IF :DEF:TX_ENABLE_FIQ_NESTING
150 IF :DEF:TX_ENABLE_IRQ_NESTING
196 IF {INTER} = {TRUE}
215 IF :DEF:TX_ENABLE_IRQ_NESTING
226 IF {INTER} = {TRUE}
281 IF :DEF:TX_ENABLE_IRQ_NESTING
291 IF :DEF:TX_ENABLE_IRQ_NESTING
[all …]
/ThreadX-v6.2.1/ports/cortex_a9/ac5/example_build/
Dtx_initialize_low_level.s35 IF :DEF:TX_ENABLE_FIQ_SUPPORT
61 IF :DEF:TX_ENABLE_FIQ_SUPPORT
65 IF :DEF:TX_ENABLE_IRQ_NESTING
69 IF :DEF:TX_ENABLE_FIQ_NESTING
99 IF {TARGET_FPU_VFP} = {TRUE}
170 IF :DEF:TX_ENABLE_IRQ_NESTING
216 IF {INTER} = {TRUE}
235 IF :DEF:TX_ENABLE_IRQ_NESTING
246 IF {INTER} = {TRUE}
301 IF :DEF:TX_ENABLE_IRQ_NESTING
[all …]
/ThreadX-v6.2.1/ports/cortex_a7/ac5/example_build/
Dtx_initialize_low_level.s35 IF :DEF:TX_ENABLE_FIQ_SUPPORT
61 IF :DEF:TX_ENABLE_FIQ_SUPPORT
65 IF :DEF:TX_ENABLE_IRQ_NESTING
69 IF :DEF:TX_ENABLE_FIQ_NESTING
99 IF {TARGET_FPU_VFP} = {TRUE}
170 IF :DEF:TX_ENABLE_IRQ_NESTING
216 IF {INTER} = {TRUE}
235 IF :DEF:TX_ENABLE_IRQ_NESTING
246 IF {INTER} = {TRUE}
301 IF :DEF:TX_ENABLE_IRQ_NESTING
[all …]

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