| /ThreadX-v6.2.1/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/ |
| D | tx_zynqmp_low_level.c | 43 #define GICD_ICENABLER(i) GIC_REG(0x180 + 4*(i)) macro
76 GICD_ICENABLER(id>>5) = 1 << (id & 0x1f); in tx_irq_default_handler()
361 GICD_ICENABLER(i) = ~0; in _tx_platform_initialize_low_level()
566 GICD_ICENABLER(id>>5) = 1 << (id & 0x1f); in tx_zynqmp_irq_disable()
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| /ThreadX-v6.2.1/ports/cortex_a55/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
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| /ThreadX-v6.2.1/ports/cortex_a57/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
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| /ThreadX-v6.2.1/ports/cortex_a34/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
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| /ThreadX-v6.2.1/ports/cortex_a65/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports/cortex_a53/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports/cortex_a35/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports/cortex_a53/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports/cortex_a35/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports/cortex_a55/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports/cortex_a72/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports/cortex_a75/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports/cortex_a75/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports/cortex_a76/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports_module/cortex_a35/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
| /ThreadX-v6.2.1/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 44 volatile uint32_t GICD_ICENABLER[32]; // +0x0180 member
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
|
