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Searched refs:FIQ_DISABLE (Results 1 – 25 of 44) sorted by relevance

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/ThreadX-v6.2.1/ports/cortex_a12/ac6/src/
Dtx_thread_fiq_nesting_start.S23 FIQ_DISABLE = 0x40 // FIQ disable bit define
90 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a12/gnu/src/
Dtx_thread_fiq_nesting_start.S26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a7/ac6/src/
Dtx_thread_fiq_nesting_start.S23 FIQ_DISABLE = 0x40 // FIQ disable bit define
90 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a17/ac6/src/
Dtx_thread_fiq_nesting_start.S23 FIQ_DISABLE = 0x40 // FIQ disable bit define
90 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a17/gnu/src/
Dtx_thread_fiq_nesting_start.S26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a8/gnu/src/
Dtx_thread_fiq_nesting_start.S26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a5/gnu/src/
Dtx_thread_fiq_nesting_start.S26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a5/ac6/src/
Dtx_thread_fiq_nesting_start.S23 FIQ_DISABLE = 0x40 // FIQ disable bit define
90 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a15/ac6/src/
Dtx_thread_fiq_nesting_start.S23 FIQ_DISABLE = 0x40 // FIQ disable bit define
90 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a15/gnu/src/
Dtx_thread_fiq_nesting_start.S26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a7/gnu/src/
Dtx_thread_fiq_nesting_start.S26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a8/ac6/src/
Dtx_thread_fiq_nesting_start.S23 FIQ_DISABLE = 0x40 // FIQ disable bit define
90 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
/ThreadX-v6.2.1/ports_module/cortex_a7/gnu/module_manager/src/
Dtx_thread_fiq_nesting_start.s23 FIQ_DISABLE = 0x40 // FIQ disable bit define
90 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a9/ac6/src/
Dtx_thread_fiq_nesting_start.S23 FIQ_DISABLE = 0x40 // FIQ disable bit define
90 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a9/gnu/src/
Dtx_thread_fiq_nesting_start.S26 FIQ_DISABLE = 0x40 // FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/arm9/iar/src/
Dtx_thread_fiq_nesting_start.s34 FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit label
95 BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a9/iar/src/
Dtx_thread_fiq_nesting_start.s34 FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit label
95 BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a5/iar/src/
Dtx_thread_fiq_nesting_start.s34 FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit label
95 BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/arm11/iar/src/
Dtx_thread_fiq_nesting_start.s34 FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit label
95 BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a7/iar/src/
Dtx_thread_fiq_nesting_start.s34 FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit label
95 BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_a8/iar/src/
Dtx_thread_fiq_nesting_start.s34 FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit label
95 BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/arm11/gnu/src/
Dtx_thread_fiq_nesting_start.S26 FIQ_DISABLE = 0x40 @ FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/arm9/gnu/src/
Dtx_thread_fiq_nesting_start.S26 FIQ_DISABLE = 0x40 @ FIQ disable bit define
96 BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_r5/gnu/src/
Dtx_thread_fiq_nesting_start.S26 FIQ_DISABLE = 0x40 @ FIQ disable bit define
93 BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR
/ThreadX-v6.2.1/ports/cortex_r4/gnu/src/
Dtx_thread_fiq_nesting_start.S26 FIQ_DISABLE = 0x40 @ FIQ disable bit define
93 BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR

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