1 /****************************************************************************** 2 TMS320C66xx KeyStone Multicore DSP Software Development Kit (SDK). Rev 2A. 3 (C) MicroLAB Systems, 2014-2015 4 5 File: Definitions 6 ----- 7 8 Notes: 9 ------ 10 1. This C-header file contains general DSP definitions and 11 is used with C66XX.h C-header file. 12 13 2. This file is best viewed with the TAB setting set to '4'. 14 15 ******************************************************************************/ 16 17 18 /** 19 * @file C66XX_DEF.hxx 20 * 21 * @brief Definitions 22 * 23 * This file contains general C66xx DSP definitions 24 * 25 */ 26 27 28 #ifndef __C66XX_DEF_HXX__ // check for this file has been already included 29 #define __C66XX_DEF_HXX__ 1 30 31 32 //============================================================================= 33 //============ DSP CPU ID ===================================================== 34 //============================================================================= 35 36 // DSP CPU ID is located at CSR register and is used to identify the chip 37 #define C66XX_DSP_CPU_ID 0x15 38 //============================================================================= 39 40 41 42 #ifdef __C66XX_SELECT_C6678_DSP__ 43 //============================================================================= 44 //============ DSP cores number =============================================== 45 //============================================================================= 46 #define C66XX_DSP_NUMBER_OF_CORES 8 47 //============================================================================= 48 49 50 //============================================================================= 51 //============ DSP memory map ================================================= 52 //============================================================================= 53 // All address ranges refer to 32-bit LOGICAL addresses!!! 54 55 // Local L2 SRAM - 512KB 56 #define C66XX_LOCAL_L2_SRAM_SADDR 0x00800000 57 #define C66XX_LOCAL_L2_SRAM_EADDR 0x0087ffff 58 #define C66XX_LOCAL_L2_SRAM_LEN (C66XX_LOCAL_L2_SRAM_EADDR - C66XX_LOCAL_L2_SRAM_SADDR + 1) 59 60 // Local L1P SRAM - 32KB 61 #define C66XX_LOCAL_L1P_SRAM_SADDR 0x00e00000 62 #define C66XX_LOCAL_L1P_SRAM_EADDR 0x00e07fff 63 #define C66XX_LOCAL_L1P_SRAM_LEN (C66XX_LOCAL_L1P_SRAM_EADDR - C66XX_LOCAL_L1P_SRAM_SADDR + 1) 64 65 // Local L1D SRAM - 32KB 66 #define C66XX_LOCAL_L1D_SRAM_SADDR 0x00f00000 67 #define C66XX_LOCAL_L1D_SRAM_EADDR 0x00f07fff 68 #define C66XX_LOCAL_L1D_SRAM_LEN (C66XX_LOCAL_L1D_SRAM_EADDR - C66XX_LOCAL_L1D_SRAM_SADDR + 1) 69 70 // C66xx CorePack registers area - 4MB 71 #define C66XX_DSP_RG_AREA_SADDR 0x01800000 72 #define C66XX_DSP_RG_AREA_EADDR 0x01bfffff 73 #define C66XX_DSP_RG_AREA_LEN (C66XX_DSP_RG_AREA_EADDR - C66XX_DSP_RG_AREA_SADDR + 1) 74 75 // Tracer MSMC 0 registers area - 128B 76 #define C66XX_TRACER_MSMC_0_RG_AREA_SADDR 0x01d00000 77 #define C66XX_TRACER_MSMC_0_RG_AREA_EADDR 0x01d0007f 78 #define C66XX_TRACER_MSMC_0_RG_AREA_LEN (C66XX_TRACER_MSMC_0_RG_AREA_EADDR - C66XX_TRACER_MSMC_0_RG_AREA_SADDR + 1) 79 80 // Tracer MSMC 1 registers area - 128B 81 #define C66XX_TRACER_MSMC_1_RG_AREA_SADDR 0x01d08000 82 #define C66XX_TRACER_MSMC_1_RG_AREA_EADDR 0x01d0807f 83 #define C66XX_TRACER_MSMC_1_RG_AREA_LEN (C66XX_TRACER_MSMC_1_RG_AREA_EADDR - C66XX_TRACER_MSMC_1_RG_AREA_SADDR + 1) 84 85 // Tracer MSMC 2 registers area - 128B 86 #define C66XX_TRACER_MSMC_2_RG_AREA_SADDR 0x01d10000 87 #define C66XX_TRACER_MSMC_2_RG_AREA_EADDR 0x01d1007f 88 #define C66XX_TRACER_MSMC_2_RG_AREA_LEN (C66XX_TRACER_MSMC_2_RG_AREA_EADDR - C66XX_TRACER_MSMC_2_RG_AREA_SADDR + 1) 89 90 // Tracer MSMC 3 registers area - 128B 91 #define C66XX_TRACER_MSMC_3_RG_AREA_SADDR 0x01d18000 92 #define C66XX_TRACER_MSMC_3_RG_AREA_EADDR 0x01d1807f 93 #define C66XX_TRACER_MSMC_3_RG_AREA_LEN (C66XX_TRACER_MSMC_3_RG_AREA_EADDR - C66XX_TRACER_MSMC_3_RG_AREA_SADDR + 1) 94 95 // Tracer QM DMA registers area - 128B 96 #define C66XX_TRACER_QM_DMA_RG_AREA_SADDR 0x01d20000 97 #define C66XX_TRACER_QM_DMA_RG_AREA_EADDR 0x01d2007f 98 #define C66XX_TRACER_QM_DMA_RG_AREA_LEN (C66XX_TRACER_QM_DMA_RG_AREA_EADDR - C66XX_TRACER_QM_DMA_RG_AREA_SADDR + 1) 99 100 // Tracer DDR registers area - 128B 101 #define C66XX_TRACER_DDR_RG_AREA_SADDR 0x01d28000 102 #define C66XX_TRACER_DDR_RG_AREA_EADDR 0x01d2807f 103 #define C66XX_TRACER_DDR_RG_AREA_LEN (C66XX_TRACER_DDR_RG_AREA_EADDR - C66XX_TRACER_DDR_RG_AREA_SADDR + 1) 104 105 // Tracer SM registers area - 128B 106 #define C66XX_TRACER_SM_RG_AREA_SADDR 0x01d30000 107 #define C66XX_TRACER_SM_RG_AREA_EADDR 0x01d3007f 108 #define C66XX_TRACER_SM_RG_AREA_LEN (C66XX_TRACER_SM_RG_AREA_EADDR - C66XX_TRACER_SM_RG_AREA_SADDR + 1) 109 110 // Tracer QM CFG registers area - 128B 111 #define C66XX_TRACER_QM_CFG_RG_AREA_SADDR 0x01d38000 112 #define C66XX_TRACER_QM_CFG_RG_AREA_EADDR 0x01d3807f 113 #define C66XX_TRACER_QM_CFG_RG_AREA_LEN (C66XX_TRACER_QM_CFG_RG_AREA_EADDR - C66XX_TRACER_QM_CFG_RG_AREA_SADDR + 1) 114 115 // Tracer CFG registers area - 128B 116 #define C66XX_TRACER_CFG_RG_AREA_SADDR 0x01d40000 117 #define C66XX_TRACER_CFG_RG_AREA_EADDR 0x01d4007f 118 #define C66XX_TRACER_CFG_RG_AREA_LEN (C66XX_TRACER_CFG_RG_AREA_EADDR - C66XX_TRACER_CFG_RG_AREA_SADDR + 1) 119 120 // Tracer L2 0 registers area - 128B 121 #define C66XX_TRACER_L2_0_RG_AREA_SADDR 0x01d48000 122 #define C66XX_TRACER_L2_0_RG_AREA_EADDR 0x01d4807f 123 #define C66XX_TRACER_L2_0_RG_AREA_LEN (C66XX_TRACER_L2_0_RG_AREA_EADDR - C66XX_TRACER_L2_0_RG_AREA_SADDR + 1) 124 125 // Tracer L2 1 registers area - 128B 126 #define C66XX_TRACER_L2_1_RG_AREA_SADDR 0x01d50000 127 #define C66XX_TRACER_L2_1_RG_AREA_EADDR 0x01d5007f 128 #define C66XX_TRACER_L2_1_RG_AREA_LEN (C66XX_TRACER_L2_1_RG_AREA_EADDR - C66XX_TRACER_L2_1_RG_AREA_SADDR + 1) 129 130 // Tracer L2 2 registers area - 128B 131 #define C66XX_TRACER_L2_2_RG_AREA_SADDR 0x01d58000 132 #define C66XX_TRACER_L2_2_RG_AREA_EADDR 0x01d5807f 133 #define C66XX_TRACER_L2_2_RG_AREA_LEN (C66XX_TRACER_L2_2_RG_AREA_EADDR - C66XX_TRACER_L2_2_RG_AREA_SADDR + 1) 134 135 // Tracer L2 3 registers area - 128B 136 #define C66XX_TRACER_L2_3_RG_AREA_SADDR 0x01d60000 137 #define C66XX_TRACER_L2_3_RG_AREA_EADDR 0x01d6007f 138 #define C66XX_TRACER_L2_3_RG_AREA_LEN (C66XX_TRACER_L2_3_RG_AREA_EADDR - C66XX_TRACER_L2_3_RG_AREA_SADDR + 1) 139 140 // Tracer L2 4 registers area - 128B 141 #define C66XX_TRACER_L2_4_RG_AREA_SADDR 0x01d68000 142 #define C66XX_TRACER_L2_4_RG_AREA_EADDR 0x01d6807f 143 #define C66XX_TRACER_L2_4_RG_AREA_LEN (C66XX_TRACER_L2_4_RG_AREA_EADDR - C66XX_TRACER_L2_4_RG_AREA_SADDR + 1) 144 145 // Tracer L2 5 registers area - 128B 146 #define C66XX_TRACER_L2_5_RG_AREA_SADDR 0x01d70000 147 #define C66XX_TRACER_L2_5_RG_AREA_EADDR 0x01d7007f 148 #define C66XX_TRACER_L2_5_RG_AREA_LEN (C66XX_TRACER_L2_5_RG_AREA_EADDR - C66XX_TRACER_L2_5_RG_AREA_SADDR + 1) 149 150 // Tracer L2 6 registers area - 128B 151 #define C66XX_TRACER_L2_6_RG_AREA_SADDR 0x01d78000 152 #define C66XX_TRACER_L2_6_RG_AREA_EADDR 0x01d7807f 153 #define C66XX_TRACER_L2_6_RG_AREA_LEN (C66XX_TRACER_L2_6_RG_AREA_EADDR - C66XX_TRACER_L2_6_RG_AREA_SADDR + 1) 154 155 // Tracer L2 7 registers area - 128B 156 #define C66XX_TRACER_L2_7_RG_AREA_SADDR 0x01d80000 157 #define C66XX_TRACER_L2_7_RG_AREA_EADDR 0x01d8007f 158 #define C66XX_TRACER_L2_7_RG_AREA_LEN (C66XX_TRACER_L2_7_RG_AREA_EADDR - C66XX_TRACER_L2_7_RG_AREA_SADDR + 1) 159 160 // Telecom Serial Interface Port (TSIP) 0 registers area - 256KB 161 #define C66XX_TSIP_0_RG_AREA_SADDR 0x01e00000 162 #define C66XX_TSIP_0_RG_AREA_EADDR 0x01e3ffff 163 #define C66XX_TSIP_0_RG_AREA_LEN (C66XX_TSIP_0_RG_AREA_EADDR - C66XX_TSIP_0_RG_AREA_SADDR + 1) 164 165 // Telecom Serial Interface Port (TSIP) 1 registers area - 256KB 166 #define C66XX_TSIP_1_RG_AREA_SADDR 0x01e80000 167 #define C66XX_TSIP_1_RG_AREA_EADDR 0x01ebffff 168 #define C66XX_TSIP_1_RG_AREA_LEN (C66XX_TSIP_1_RG_AREA_EADDR - C66XX_TSIP_1_RG_AREA_SADDR + 1) 169 170 // Network Coprocessor (NETCP) registers area - 1MB 171 #define C66XX_NETCP_RG_AREA_SADDR 0x02000000 172 #define C66XX_NETCP_RG_AREA_EADDR 0x020fffff 173 #define C66XX_NETCP_RG_AREA_LEN (C66XX_NETCP_RG_AREA_EADDR - C66XX_NETCP_RG_AREA_SADDR + 1) 174 175 // Timer0 registers area - 128B 176 #define C66XX_TIMER_0_RG_AREA_SADDR 0x02200000 177 #define C66XX_TIMER_0_RG_AREA_EADDR 0x0220007f 178 #define C66XX_TIMER_0_RG_AREA_LEN (C66XX_TIMER_0_RG_AREA_EADDR - C66XX_TIMER_0_RG_AREA_SADDR + 1) 179 180 // Timer1 registers area - 128B 181 #define C66XX_TIMER_1_RG_AREA_SADDR 0x02210000 182 #define C66XX_TIMER_1_RG_AREA_EADDR 0x0221007f 183 #define C66XX_TIMER_1_RG_AREA_LEN (C66XX_TIMER_1_RG_AREA_EADDR - C66XX_TIMER_1_RG_AREA_SADDR + 1) 184 185 // Timer2 registers area - 128B 186 #define C66XX_TIMER_2_RG_AREA_SADDR 0x02220000 187 #define C66XX_TIMER_2_RG_AREA_EADDR 0x0222007f 188 #define C66XX_TIMER_2_RG_AREA_LEN (C66XX_TIMER_2_RG_AREA_EADDR - C66XX_TIMER_2_RG_AREA_SADDR + 1) 189 190 // Timer3 registers area - 128B 191 #define C66XX_TIMER_3_RG_AREA_SADDR 0x02230000 192 #define C66XX_TIMER_3_RG_AREA_EADDR 0x0223007f 193 #define C66XX_TIMER_3_RG_AREA_LEN (C66XX_TIMER_3_RG_AREA_EADDR - C66XX_TIMER_3_RG_AREA_SADDR + 1) 194 195 // Timer4 registers area - 128B 196 #define C66XX_TIMER_4_RG_AREA_SADDR 0x02240000 197 #define C66XX_TIMER_4_RG_AREA_EADDR 0x0224007f 198 #define C66XX_TIMER_4_RG_AREA_LEN (C66XX_TIMER_4_RG_AREA_EADDR - C66XX_TIMER_4_RG_AREA_SADDR + 1) 199 200 // Timer5 registers area - 128B 201 #define C66XX_TIMER_5_RG_AREA_SADDR 0x02250000 202 #define C66XX_TIMER_5_RG_AREA_EADDR 0x0225007f 203 #define C66XX_TIMER_5_RG_AREA_LEN (C66XX_TIMER_5_RG_AREA_EADDR - C66XX_TIMER_5_RG_AREA_SADDR + 1) 204 205 // Timer6 registers area - 128B 206 #define C66XX_TIMER_6_RG_AREA_SADDR 0x02260000 207 #define C66XX_TIMER_6_RG_AREA_EADDR 0x0226007f 208 #define C66XX_TIMER_6_RG_AREA_LEN (C66XX_TIMER_6_RG_AREA_EADDR - C66XX_TIMER_6_RG_AREA_SADDR + 1) 209 210 // Timer7 registers area - 128B 211 #define C66XX_TIMER_7_RG_AREA_SADDR 0x02270000 212 #define C66XX_TIMER_7_RG_AREA_EADDR 0x0227007f 213 #define C66XX_TIMER_7_RG_AREA_LEN (C66XX_TIMER_7_RG_AREA_EADDR - C66XX_TIMER_7_RG_AREA_SADDR + 1) 214 215 // Timer8 registers area - 128B 216 #define C66XX_TIMER_8_RG_AREA_SADDR 0x02280000 217 #define C66XX_TIMER_8_RG_AREA_EADDR 0x0228007f 218 #define C66XX_TIMER_8_RG_AREA_LEN (C66XX_TIMER_8_RG_AREA_EADDR - C66XX_TIMER_8_RG_AREA_SADDR + 1) 219 220 // Timer9 registers area - 128B 221 #define C66XX_TIMER_9_RG_AREA_SADDR 0x02290000 222 #define C66XX_TIMER_9_RG_AREA_EADDR 0x0229007f 223 #define C66XX_TIMER_9_RG_AREA_LEN (C66XX_TIMER_9_RG_AREA_EADDR - C66XX_TIMER_9_RG_AREA_SADDR + 1) 224 225 // Timer10 registers area - 128B 226 #define C66XX_TIMER_10_RG_AREA_SADDR 0x022a0000 227 #define C66XX_TIMER_10_RG_AREA_EADDR 0x022a007f 228 #define C66XX_TIMER_10_RG_AREA_LEN (C66XX_TIMER_10_RG_AREA_EADDR - C66XX_TIMER_10_RG_AREA_SADDR + 1) 229 230 // Timer11 registers area - 128B 231 #define C66XX_TIMER_11_RG_AREA_SADDR 0x022b0000 232 #define C66XX_TIMER_11_RG_AREA_EADDR 0x022b007f 233 #define C66XX_TIMER_11_RG_AREA_LEN (C66XX_TIMER_11_RG_AREA_EADDR - C66XX_TIMER_11_RG_AREA_SADDR + 1) 234 235 // Timer12 registers area - 128B 236 #define C66XX_TIMER_12_RG_AREA_SADDR 0x022c0000 237 #define C66XX_TIMER_12_RG_AREA_EADDR 0x022c007f 238 #define C66XX_TIMER_12_RG_AREA_LEN (C66XX_TIMER_12_RG_AREA_EADDR - C66XX_TIMER_12_RG_AREA_SADDR + 1) 239 240 // Timer13 registers area - 128B 241 #define C66XX_TIMER_13_RG_AREA_SADDR 0x022d0000 242 #define C66XX_TIMER_13_RG_AREA_EADDR 0x022d007f 243 #define C66XX_TIMER_13_RG_AREA_LEN (C66XX_TIMER_13_RG_AREA_EADDR - C66XX_TIMER_13_RG_AREA_SADDR + 1) 244 245 // Timer14 registers area - 128B 246 #define C66XX_TIMER_14_RG_AREA_SADDR 0x022e0000 247 #define C66XX_TIMER_14_RG_AREA_EADDR 0x022e007f 248 #define C66XX_TIMER_14_RG_AREA_LEN (C66XX_TIMER_14_RG_AREA_EADDR - C66XX_TIMER_14_RG_AREA_SADDR + 1) 249 250 // Timer15 registers area - 128B 251 #define C66XX_TIMER_15_RG_AREA_SADDR 0x022f0000 252 #define C66XX_TIMER_15_RG_AREA_EADDR 0x022f007f 253 #define C66XX_TIMER_15_RG_AREA_LEN (C66XX_TIMER_15_RG_AREA_EADDR - C66XX_TIMER_15_RG_AREA_SADDR + 1) 254 255 // PLL controller registers area - 512B 256 #define C66XX_PLL_RG_AREA_SADDR 0x02310000 257 #define C66XX_PLL_RG_AREA_EADDR 0x023101ff 258 #define C66XX_PLL_RG_AREA_LEN (C66XX_PLL_RG_AREA_EADDR - C66XX_PLL_RG_AREA_SADDR + 1) 259 260 // GPIO registers area - 256B 261 #define C66XX_GPIO_RG_AREA_SADDR 0x02320000 262 #define C66XX_GPIO_RG_AREA_EADDR 0x023200ff 263 #define C66XX_GPIO_RG_AREA_LEN (C66XX_GPIO_RG_AREA_EADDR - C66XX_GPIO_RG_AREA_SADDR + 1) 264 265 // SmartReflex registers area - 256B 266 #define C66XX_SMARTREFLEX_RG_AREA_SADDR 0x02330000 267 #define C66XX_SMARTREFLEX_RG_AREA_EADDR 0x023303ff 268 #define C66XX_SMARTREFLEX_RG_AREA_LEN (C66XX_SMARTREFLEX_RG_AREA_EADDR - C66XX_SMARTREFLEX_RG_AREA_SADDR + 1) 269 270 // Power Sleep Controller (PSC) registers area - 4KB 271 #define C66XX_PSC_RG_AREA_SADDR 0x02350000 272 #define C66XX_PSC_RG_AREA_EADDR 0x02350fff 273 #define C66XX_PSC_RG_AREA_LEN (C66XX_PSC_RG_AREA_EADDR - C66XX_PSC_RG_AREA_SADDR + 1) 274 275 // Memory Protection Unit (MPU) 0 registers area - 1KB 276 #define C66XX_MPU_0_RG_AREA_SADDR 0x02360000 277 #define C66XX_MPU_0_RG_AREA_EADDR 0x023603ff 278 #define C66XX_MPU_0_RG_AREA_LEN (C66XX_MPU_0_RG_AREA_EADDR - C66XX_MPU_0_RG_AREA_SADDR + 1) 279 280 // Memory Protection Unit (MPU) 1 registers area - 1KB 281 #define C66XX_MPU_1_RG_AREA_SADDR 0x02368000 282 #define C66XX_MPU_1_RG_AREA_EADDR 0x023683ff 283 #define C66XX_MPU_1_RG_AREA_LEN (C66XX_MPU_1_RG_AREA_EADDR - C66XX_MPU_1_RG_AREA_SADDR + 1) 284 285 // Memory Protection Unit (MPU) 2 registers area - 1KB 286 #define C66XX_MPU_2_RG_AREA_SADDR 0x02370000 287 #define C66XX_MPU_2_RG_AREA_EADDR 0x023703ff 288 #define C66XX_MPU_2_RG_AREA_LEN (C66XX_MPU_2_RG_AREA_EADDR - C66XX_MPU_2_RG_AREA_SADDR + 1) 289 290 // Memory Protection Unit (MPU) 3 registers area - 1KB 291 #define C66XX_MPU_3_RG_AREA_SADDR 0x02378000 292 #define C66XX_MPU_3_RG_AREA_EADDR 0x023783ff 293 #define C66XX_MPU_3_RG_AREA_LEN (C66XX_MPU_3_RG_AREA_EADDR - C66XX_MPU_3_RG_AREA_SADDR + 1) 294 295 // Debug subsystem configuration registers area - 256KB 296 #define C66XX_DEBUG_CFG_RG_AREA_SADDR 0x02400000 297 #define C66XX_DEBUG_CFG_RG_AREA_EADDR 0x0243ffff 298 #define C66XX_DEBUG_CFG_RG_AREA_LEN (C66XX_DEBUG_CFG_RG_AREA_EADDR - C66XX_DEBUG_CFG_RG_AREA_SADDR + 1) 299 300 // DSP trace formatter 0 registers area - 16KB 301 #define C66XX_DSP_TRACE_FORMATTER_0_RG_AREA_SADDR 0x02440000 302 #define C66XX_DSP_TRACE_FORMATTER_0_RG_AREA_EADDR 0x02443fff 303 #define C66XX_DSP_TRACE_FORMATTER_0_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_0_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_0_RG_AREA_SADDR + 1) 304 305 // DSP trace formatter 1 registers area - 16KB 306 #define C66XX_DSP_TRACE_FORMATTER_1_RG_AREA_SADDR 0x02450000 307 #define C66XX_DSP_TRACE_FORMATTER_1_RG_AREA_EADDR 0x02453fff 308 #define C66XX_DSP_TRACE_FORMATTER_1_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_1_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_1_RG_AREA_SADDR + 1) 309 310 // DSP trace formatter 2 registers area - 16KB 311 #define C66XX_DSP_TRACE_FORMATTER_2_RG_AREA_SADDR 0x02460000 312 #define C66XX_DSP_TRACE_FORMATTER_2_RG_AREA_EADDR 0x02463fff 313 #define C66XX_DSP_TRACE_FORMATTER_2_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_2_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_2_RG_AREA_SADDR + 1) 314 315 // DSP trace formatter 3 registers area - 16KB 316 #define C66XX_DSP_TRACE_FORMATTER_3_RG_AREA_SADDR 0x02470000 317 #define C66XX_DSP_TRACE_FORMATTER_3_RG_AREA_EADDR 0x02473fff 318 #define C66XX_DSP_TRACE_FORMATTER_3_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_3_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_3_RG_AREA_SADDR + 1) 319 320 // DSP trace formatter 4 registers area - 16KB 321 #define C66XX_DSP_TRACE_FORMATTER_4_RG_AREA_SADDR 0x02480000 322 #define C66XX_DSP_TRACE_FORMATTER_4_RG_AREA_EADDR 0x02483fff 323 #define C66XX_DSP_TRACE_FORMATTER_4_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_4_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_4_RG_AREA_SADDR + 1) 324 325 // DSP trace formatter 5 registers area - 16KB 326 #define C66XX_DSP_TRACE_FORMATTER_5_RG_AREA_SADDR 0x02490000 327 #define C66XX_DSP_TRACE_FORMATTER_5_RG_AREA_EADDR 0x02493fff 328 #define C66XX_DSP_TRACE_FORMATTER_5_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_5_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_5_RG_AREA_SADDR + 1) 329 330 // DSP trace formatter 6 registers area - 16KB 331 #define C66XX_DSP_TRACE_FORMATTER_6_RG_AREA_SADDR 0x024a0000 332 #define C66XX_DSP_TRACE_FORMATTER_6_RG_AREA_EADDR 0x024a3fff 333 #define C66XX_DSP_TRACE_FORMATTER_6_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_6_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_6_RG_AREA_SADDR + 1) 334 335 // DSP trace formatter 7 registers area - 16KB 336 #define C66XX_DSP_TRACE_FORMATTER_7_RG_AREA_SADDR 0x024b0000 337 #define C66XX_DSP_TRACE_FORMATTER_7_RG_AREA_EADDR 0x024b3fff 338 #define C66XX_DSP_TRACE_FORMATTER_7_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_7_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_7_RG_AREA_SADDR + 1) 339 340 // I2C registers area - 128B 341 #define C66XX_I2C_RG_AREA_SADDR 0x02530000 342 #define C66XX_I2C_RG_AREA_EADDR 0x0253007f 343 #define C66XX_I2C_RG_AREA_LEN (C66XX_I2C_RG_AREA_EADDR - C66XX_I2C_RG_AREA_SADDR + 1) 344 345 // UART registers area - 64B 346 #define C66XX_UART_RG_AREA_SADDR 0x02540000 347 #define C66XX_UART_RG_AREA_EADDR 0x0254003f 348 #define C66XX_UART_RG_AREA_LEN (C66XX_UART_RG_AREA_EADDR - C66XX_UART_RG_AREA_SADDR + 1) 349 350 // Chip Interrupt Controller (CIC) 0 registers area - 8KB 351 #define C66XX_CIC_0_RG_AREA_SADDR 0x02600000 352 #define C66XX_CIC_0_RG_AREA_EADDR 0x02601fff 353 #define C66XX_CIC_0_RG_AREA_LEN (C66XX_CIC_0_RG_AREA_EADDR - C66XX_CIC_0_RG_AREA_SADDR + 1) 354 355 // Chip Interrupt Controller (CIC) 1 registers area - 8KB 356 #define C66XX_CIC_1_RG_AREA_SADDR 0x02604000 357 #define C66XX_CIC_1_RG_AREA_EADDR 0x02605fff 358 #define C66XX_CIC_1_RG_AREA_LEN (C66XX_CIC_1_RG_AREA_EADDR - C66XX_CIC_1_RG_AREA_SADDR + 1) 359 360 // Chip Interrupt Controller (CIC) 2 registers area - 8KB 361 #define C66XX_CIC_2_RG_AREA_SADDR 0x02608000 362 #define C66XX_CIC_2_RG_AREA_EADDR 0x02609fff 363 #define C66XX_CIC_2_RG_AREA_LEN (C66XX_CIC_2_RG_AREA_EADDR - C66XX_CIC_2_RG_AREA_SADDR + 1) 364 365 // Chip Interrupt Controller (CIC) 3 registers area - 8KB 366 #define C66XX_CIC_3_RG_AREA_SADDR 0x0260c000 367 #define C66XX_CIC_3_RG_AREA_EADDR 0x0260dfff 368 #define C66XX_CIC_3_RG_AREA_LEN (C66XX_CIC_3_RG_AREA_EADDR - C66XX_CIC_3_RG_AREA_SADDR + 1) 369 370 // Device State Control registers area - 2KB 371 #define C66XX_BOOTCFG_RG_AREA_SADDR 0x02620000 372 #define C66XX_BOOTCFG_RG_AREA_EADDR 0x026207ff 373 #define C66XX_BOOTCFG_RG_AREA_LEN (C66XX_BOOTCFG_RG_AREA_EADDR - C66XX_BOOTCFG_RG_AREA_SADDR + 1) 374 375 // Semaphore (SEM) registers area - 2KB 376 #define C66XX_SEM_RG_AREA_SADDR 0x02640000 377 #define C66XX_SEM_RG_AREA_EADDR 0x026407ff 378 #define C66XX_SEM_RG_AREA_LEN (C66XX_SEM_RG_AREA_EADDR - C66XX_SEM_RG_AREA_SADDR + 1) 379 380 // EDMA3 Channel Controller (EDMA3CC) 0 registers area - 32KB 381 #define C66XX_EDMA3CC_0_RG_AREA_SADDR 0x02700000 382 #define C66XX_EDMA3CC_0_RG_AREA_EADDR 0x02707fff 383 #define C66XX_EDMA3CC_0_RG_AREA_LEN (C66XX_EDMA3CC_0_RG_AREA_EADDR - C66XX_EDMA3CC_0_RG_AREA_SADDR + 1) 384 385 // EDMA3 Channel Controller (EDMA3CC) 1 registers area - 32KB 386 #define C66XX_EDMA3CC_1_RG_AREA_SADDR 0x02720000 387 #define C66XX_EDMA3CC_1_RG_AREA_EADDR 0x02727fff 388 #define C66XX_EDMA3CC_1_RG_AREA_LEN (C66XX_EDMA3CC_1_RG_AREA_EADDR - C66XX_EDMA3CC_1_RG_AREA_SADDR + 1) 389 390 // EDMA3 Channel Controller (EDMA3CC) 2 registers area - 32KB 391 #define C66XX_EDMA3CC_2_RG_AREA_SADDR 0x02740000 392 #define C66XX_EDMA3CC_2_RG_AREA_EADDR 0x02747fff 393 #define C66XX_EDMA3CC_2_RG_AREA_LEN (C66XX_EDMA3CC_2_RG_AREA_EADDR - C66XX_EDMA3CC_2_RG_AREA_SADDR + 1) 394 395 // EDMA3CC0 Transfer Controller (EDMA3TC) 0 registers area - 1KB 396 #define C66XX_EDMA3CC_0_TC_0_RG_AREA_SADDR 0x02760000 397 #define C66XX_EDMA3CC_0_TC_0_RG_AREA_EADDR 0x027603ff 398 #define C66XX_EDMA3CC_0_TC_0_RG_AREA_LEN (C66XX_EDMA3CC_0_TC_0_RG_AREA_EADDR - C66XX_EDMA3CC_0_TC_0_RG_AREA_SADDR + 1) 399 400 // EDMA3CC0 Transfer Controller (EDMA3TC) 1 registers area - 1KB 401 #define C66XX_EDMA3CC_0_TC_1_RG_AREA_SADDR 0x02768000 402 #define C66XX_EDMA3CC_0_TC_1_RG_AREA_EADDR 0x027683ff 403 #define C66XX_EDMA3CC_0_TC_1_RG_AREA_LEN (C66XX_EDMA3CC_0_TC_1_RG_AREA_EADDR - C66XX_EDMA3CC_0_TC_1_RG_AREA_SADDR + 1) 404 405 // EDMA3CC1 Transfer Controller (EDMA3TC) 0 registers area - 1KB 406 #define C66XX_EDMA3CC_1_TC_0_RG_AREA_SADDR 0x02770000 407 #define C66XX_EDMA3CC_1_TC_0_RG_AREA_EADDR 0x027703ff 408 #define C66XX_EDMA3CC_1_TC_0_RG_AREA_LEN (C66XX_EDMA3CC_1_TC_0_RG_AREA_EADDR - C66XX_EDMA3CC_1_TC_0_RG_AREA_SADDR + 1) 409 410 // EDMA3CC1 Transfer Controller (EDMA3TC) 1 registers area - 1KB 411 #define C66XX_EDMA3CC_1_TC_1_RG_AREA_SADDR 0x02778000 412 #define C66XX_EDMA3CC_1_TC_1_RG_AREA_EADDR 0x027783ff 413 #define C66XX_EDMA3CC_1_TC_1_RG_AREA_LEN (C66XX_EDMA3CC_1_TC_1_RG_AREA_EADDR - C66XX_EDMA3CC_1_TC_1_RG_AREA_SADDR + 1) 414 415 // EDMA3CC1 Transfer Controller (EDMA3TC) 2 registers area - 1KB 416 #define C66XX_EDMA3CC_1_TC_2_RG_AREA_SADDR 0x02780000 417 #define C66XX_EDMA3CC_1_TC_2_RG_AREA_EADDR 0x027803ff 418 #define C66XX_EDMA3CC_1_TC_2_RG_AREA_LEN (C66XX_EDMA3CC_1_TC_2_RG_AREA_EADDR - C66XX_EDMA3CC_1_TC_2_RG_AREA_SADDR + 1) 419 420 // EDMA3CC1 Transfer Controller (EDMA3TC) 3 registers area - 1KB 421 #define C66XX_EDMA3CC_1_TC_3_RG_AREA_SADDR 0x02788000 422 #define C66XX_EDMA3CC_1_TC_3_RG_AREA_EADDR 0x027883ff 423 #define C66XX_EDMA3CC_1_TC_3_RG_AREA_LEN (C66XX_EDMA3CC_1_TC_3_RG_AREA_EADDR - C66XX_EDMA3CC_1_TC_3_RG_AREA_SADDR + 1) 424 425 // EDMA3CC2 Transfer Controller (EDMA3TC) 0 registers area - 1KB 426 #define C66XX_EDMA3CC_2_TC_0_RG_AREA_SADDR 0x02790000 427 #define C66XX_EDMA3CC_2_TC_0_RG_AREA_EADDR 0x027903ff 428 #define C66XX_EDMA3CC_2_TC_0_RG_AREA_LEN (C66XX_EDMA3CC_2_TC_0_RG_AREA_EADDR - C66XX_EDMA3CC_2_TC_0_RG_AREA_SADDR + 1) 429 430 // EDMA3CC2 Transfer Controller (EDMA3TC) 1 registers area - 1KB 431 #define C66XX_EDMA3CC_2_TC_1_RG_AREA_SADDR 0x02798000 432 #define C66XX_EDMA3CC_2_TC_1_RG_AREA_EADDR 0x027983ff 433 #define C66XX_EDMA3CC_2_TC_1_RG_AREA_LEN (C66XX_EDMA3CC_2_TC_1_RG_AREA_EADDR - C66XX_EDMA3CC_2_TC_1_RG_AREA_SADDR + 1) 434 435 // EDMA3CC2 Transfer Controller (EDMA3TC) 2 registers area - 1KB 436 #define C66XX_EDMA3CC_2_TC_2_RG_AREA_SADDR 0x027a0000 437 #define C66XX_EDMA3CC_2_TC_2_RG_AREA_EADDR 0x027a03ff 438 #define C66XX_EDMA3CC_2_TC_2_RG_AREA_LEN (C66XX_EDMA3CC_2_TC_2_RG_AREA_EADDR - C66XX_EDMA3CC_2_TC_2_RG_AREA_SADDR + 1) 439 440 // EDMA3CC2 Transfer Controller (EDMA3TC) 3 registers area - 1KB 441 #define C66XX_EDMA3CC_2_TC_3_RG_AREA_SADDR 0x027a8000 442 #define C66XX_EDMA3CC_2_TC_3_RG_AREA_EADDR 0x027a83ff 443 #define C66XX_EDMA3CC_2_TC_3_RG_AREA_LEN (C66XX_EDMA3CC_2_TC_3_RG_AREA_EADDR - C66XX_EDMA3CC_2_TC_3_RG_AREA_SADDR + 1) 444 445 // TI embedded trace buffer (TETB) CorePac0 registers area - 4KB 446 #define C66XX_TETB_0_RG_AREA_SADDR 0x027d0000 447 #define C66XX_TETB_0_RG_AREA_EADDR 0x027d0fff 448 #define C66XX_TETB_0_RG_AREA_LEN (C66XX_TETB_0_RG_AREA_EADDR - C66XX_TETB_0_RG_AREA_SADDR + 1) 449 450 // TI embedded trace buffer (TETB) CorePac1 registers area - 4KB 451 #define C66XX_TETB_1_RG_AREA_SADDR 0x027e0000 452 #define C66XX_TETB_1_RG_AREA_EADDR 0x027e0fff 453 #define C66XX_TETB_1_RG_AREA_LEN (C66XX_TETB_1_RG_AREA_EADDR - C66XX_TETB_1_RG_AREA_SADDR + 1) 454 455 // TI embedded trace buffer (TETB) CorePac2 registers area - 4KB 456 #define C66XX_TETB_2_RG_AREA_SADDR 0x027f0000 457 #define C66XX_TETB_2_RG_AREA_EADDR 0x027f0fff 458 #define C66XX_TETB_2_RG_AREA_LEN (C66XX_TETB_2_RG_AREA_EADDR - C66XX_TETB_2_RG_AREA_SADDR + 1) 459 460 // TI embedded trace buffer (TETB) CorePac3 registers area - 4KB 461 #define C66XX_TETB_3_RG_AREA_SADDR 0x02800000 462 #define C66XX_TETB_3_RG_AREA_EADDR 0x02800fff 463 #define C66XX_TETB_3_RG_AREA_LEN (C66XX_TETB_3_RG_AREA_EADDR - C66XX_TETB_3_RG_AREA_SADDR + 1) 464 465 // TI embedded trace buffer (TETB) CorePac4 registers area - 4KB 466 #define C66XX_TETB_4_RG_AREA_SADDR 0x02810000 467 #define C66XX_TETB_4_RG_AREA_EADDR 0x02810fff 468 #define C66XX_TETB_4_RG_AREA_LEN (C66XX_TETB_4_RG_AREA_EADDR - C66XX_TETB_4_RG_AREA_SADDR + 1) 469 470 // TI embedded trace buffer (TETB) CorePac5 registers area - 4KB 471 #define C66XX_TETB_5_RG_AREA_SADDR 0x02820000 472 #define C66XX_TETB_5_RG_AREA_EADDR 0x02820fff 473 #define C66XX_TETB_5_RG_AREA_LEN (C66XX_TETB_5_RG_AREA_EADDR - C66XX_TETB_5_RG_AREA_SADDR + 1) 474 475 // TI embedded trace buffer (TETB) CorePac6 registers area - 4KB 476 #define C66XX_TETB_6_RG_AREA_SADDR 0x02830000 477 #define C66XX_TETB_6_RG_AREA_EADDR 0x02830fff 478 #define C66XX_TETB_6_RG_AREA_LEN (C66XX_TETB_6_RG_AREA_EADDR - C66XX_TETB_6_RG_AREA_SADDR + 1) 479 480 // TI embedded trace buffer (TETB) CorePac7 registers area - 4KB 481 #define C66XX_TETB_7_RG_AREA_SADDR 0x02840000 482 #define C66XX_TETB_7_RG_AREA_EADDR 0x02840fff 483 #define C66XX_TETB_7_RG_AREA_LEN (C66XX_TETB_7_RG_AREA_EADDR - C66XX_TETB_7_RG_AREA_SADDR + 1) 484 485 // TI embedded trace buffer (TETB) system registers area - 32KB 486 #define C66XX_TETB_SYSTEM_RG_AREA_SADDR 0x02850000 487 #define C66XX_TETB_SYSTEM_RG_AREA_EADDR 0x02857fff 488 #define C66XX_TETB_SYSTEM_RG_AREA_LEN (C66XX_TETB_SYSTEM_RG_AREA_EADDR - C66XX_TETB_SYSTEM_RG_AREA_SADDR + 1) 489 490 // Serial RapidIO (SRIO) configuration registers area - 132KB 491 #define C66XX_SRIO_RG_AREA_SADDR 0x02900000 492 #define C66XX_SRIO_RG_AREA_EADDR 0x02920fff 493 #define C66XX_SRIO_RG_AREA_LEN (C66XX_SRIO_RG_AREA_EADDR - C66XX_SRIO_RG_AREA_SADDR + 1) 494 495 // Queue manager subsystem (QMSS) configuration registers area - 2MB 496 #define C66XX_QMSS_RG_AREA_SADDR 0x02a00000 497 #define C66XX_QMSS_RG_AREA_EADDR 0x02bfffff 498 #define C66XX_QMSS_RG_AREA_LEN (C66XX_QMSS_RG_AREA_EADDR - C66XX_QMSS_RG_AREA_SADDR + 1) 499 500 // Extended memory controller (XMC) configuration registers area - 64KB 501 #define C66XX_XMC_RG_AREA_SADDR 0x08000000 502 #define C66XX_XMC_RG_AREA_EADDR 0x0800ffff 503 #define C66XX_XMC_RG_AREA_LEN (C66XX_XMC_RG_AREA_EADDR - C66XX_XMC_RG_AREA_SADDR + 1) 504 505 // Multicore shared memory controller (MSMC) configuration registers area - 1MB 506 #define C66XX_MSMC_RG_AREA_SADDR 0x0bc00000 507 #define C66XX_MSMC_RG_AREA_EADDR 0x0bcfffff 508 #define C66XX_MSMC_RG_AREA_LEN (C66XX_MSMC_RG_AREA_EADDR - C66XX_MSMC_RG_AREA_SADDR + 1) 509 510 // Multicore shared memory (MSM) area - 4MB 511 #define C66XX_MSM_SRAM_AREA_SADDR 0x0c000000 512 #define C66XX_MSM_SRAM_AREA_EADDR 0x0c3fffff 513 #define C66XX_MSM_SRAM_AREA_LEN (C66XX_MSM_SRAM_AREA_EADDR - C66XX_MSM_SRAM_AREA_SADDR + 1) 514 515 // CorePac0 L2 SRAM (address to access from external masters) - 512KB 516 #define C66XX_DSP_0_L2_SRAM_SADDR 0x10800000 517 #define C66XX_DSP_0_L2_SRAM_EADDR 0x1087ffff 518 #define C66XX_DSP_0_L2_SRAM_LEN (C66XX_DSP_0_L2_SRAM_EADDR - C66XX_DSP_0_L2_SRAM_SADDR + 1) 519 520 // CorePac0 L1P SRAM - 32KB 521 #define C66XX_DSP_0_L1P_SRAM_SADDR 0x10e00000 522 #define C66XX_DSP_0_L1P_SRAM_EADDR 0x10e07fff 523 #define C66XX_DSP_0_L1P_SRAM_LEN (C66XX_DSP_0_L1P_SRAM_EADDR - C66XX_DSP_0_L1P_SRAM_SADDR + 1) 524 525 // CorePac0 L1D SRAM - 32KB 526 #define C66XX_DSP_0_L1D_SRAM_SADDR 0x10f00000 527 #define C66XX_DSP_0_L1D_SRAM_EADDR 0x10f07fff 528 #define C66XX_DSP_0_L1D_SRAM_LEN (C66XX_DSP_0_L1D_SRAM_EADDR - C66XX_DSP_0_L1D_SRAM_SADDR + 1) 529 530 // CorePac1 L2 SRAM (address to access from external masters) - 512KB 531 #define C66XX_DSP_1_L2_SRAM_SADDR 0x11800000 532 #define C66XX_DSP_1_L2_SRAM_EADDR 0x1187ffff 533 #define C66XX_DSP_1_L2_SRAM_LEN (C66XX_DSP_1_L2_SRAM_EADDR - C66XX_DSP_1_L2_SRAM_SADDR + 1) 534 535 // CorePac1 L1P SRAM - 32KB 536 #define C66XX_DSP_1_L1P_SRAM_SADDR 0x11e00000 537 #define C66XX_DSP_1_L1P_SRAM_EADDR 0x11e07fff 538 #define C66XX_DSP_1_L1P_SRAM_LEN (C66XX_DSP_1_L1P_SRAM_EADDR - C66XX_DSP_1_L1P_SRAM_SADDR + 1) 539 540 // CorePac1 L1D SRAM - 32KB 541 #define C66XX_DSP_1_L1D_SRAM_SADDR 0x11f00000 542 #define C66XX_DSP_1_L1D_SRAM_EADDR 0x11f07fff 543 #define C66XX_DSP_1_L1D_SRAM_LEN (C66XX_DSP_1_L1D_SRAM_EADDR - C66XX_DSP_1_L1D_SRAM_SADDR + 1) 544 545 // CorePac2 L2 SRAM (address to access from external masters) - 512KB 546 #define C66XX_DSP_2_L2_SRAM_SADDR 0x12800000 547 #define C66XX_DSP_2_L2_SRAM_EADDR 0x1287ffff 548 #define C66XX_DSP_2_L2_SRAM_LEN (C66XX_DSP_2_L2_SRAM_EADDR - C66XX_DSP_2_L2_SRAM_SADDR + 1) 549 550 // CorePac2 L1P SRAM - 32KB 551 #define C66XX_DSP_2_L1P_SRAM_SADDR 0x12e00000 552 #define C66XX_DSP_2_L1P_SRAM_EADDR 0x12e07fff 553 #define C66XX_DSP_2_L1P_SRAM_LEN (C66XX_DSP_2_L1P_SRAM_EADDR - C66XX_DSP_2_L1P_SRAM_SADDR + 1) 554 555 // CorePac2 L1D SRAM - 32KB 556 #define C66XX_DSP_2_L1D_SRAM_SADDR 0x12f00000 557 #define C66XX_DSP_2_L1D_SRAM_EADDR 0x12f07fff 558 #define C66XX_DSP_2_L1D_SRAM_LEN (C66XX_DSP_2_L1D_SRAM_EADDR - C66XX_DSP_2_L1D_SRAM_SADDR + 1) 559 560 // CorePac3 L2 SRAM (address to access from external masters) - 512KB 561 #define C66XX_DSP_3_L2_SRAM_SADDR 0x13800000 562 #define C66XX_DSP_3_L2_SRAM_EADDR 0x1387ffff 563 #define C66XX_DSP_3_L2_SRAM_LEN (C66XX_DSP_3_L2_SRAM_EADDR - C66XX_DSP_3_L2_SRAM_SADDR + 1) 564 565 // CorePac3 L1P SRAM - 32KB 566 #define C66XX_DSP_3_L1P_SRAM_SADDR 0x13e00000 567 #define C66XX_DSP_3_L1P_SRAM_EADDR 0x13e07fff 568 #define C66XX_DSP_3_L1P_SRAM_LEN (C66XX_DSP_3_L1P_SRAM_EADDR - C66XX_DSP_3_L1P_SRAM_SADDR + 1) 569 570 // CorePac3 L1D SRAM - 32KB 571 #define C66XX_DSP_3_L1D_SRAM_SADDR 0x13f00000 572 #define C66XX_DSP_3_L1D_SRAM_EADDR 0x13f07fff 573 #define C66XX_DSP_3_L1D_SRAM_LEN (C66XX_DSP_3_L1D_SRAM_EADDR - C66XX_DSP_3_L1D_SRAM_SADDR + 1) 574 575 // CorePac4 L2 SRAM (address to access from external masters) - 512KB 576 #define C66XX_DSP_4_L2_SRAM_SADDR 0x14800000 577 #define C66XX_DSP_4_L2_SRAM_EADDR 0x1487ffff 578 #define C66XX_DSP_4_L2_SRAM_LEN (C66XX_DSP_4_L2_SRAM_EADDR - C66XX_DSP_4_L2_SRAM_SADDR + 1) 579 580 // CorePac4 L1P SRAM - 32KB 581 #define C66XX_DSP_4_L1P_SRAM_SADDR 0x14e00000 582 #define C66XX_DSP_4_L1P_SRAM_EADDR 0x14e07fff 583 #define C66XX_DSP_4_L1P_SRAM_LEN (C66XX_DSP_4_L1P_SRAM_EADDR - C66XX_DSP_4_L1P_SRAM_SADDR + 1) 584 585 // CorePac4 L1D SRAM - 32KB 586 #define C66XX_DSP_4_L1D_SRAM_SADDR 0x14f00000 587 #define C66XX_DSP_4_L1D_SRAM_EADDR 0x14f07fff 588 #define C66XX_DSP_4_L1D_SRAM_LEN (C66XX_DSP_4_L1D_SRAM_EADDR - C66XX_DSP_4_L1D_SRAM_SADDR + 1) 589 590 // CorePac5 L2 SRAM (address to access from external masters) - 512KB 591 #define C66XX_DSP_5_L2_SRAM_SADDR 0x15800000 592 #define C66XX_DSP_5_L2_SRAM_EADDR 0x1587ffff 593 #define C66XX_DSP_5_L2_SRAM_LEN (C66XX_DSP_5_L2_SRAM_EADDR - C66XX_DSP_5_L2_SRAM_SADDR + 1) 594 595 // CorePac5 L1P SRAM - 32KB 596 #define C66XX_DSP_5_L1P_SRAM_SADDR 0x15e00000 597 #define C66XX_DSP_5_L1P_SRAM_EADDR 0x15e07fff 598 #define C66XX_DSP_5_L1P_SRAM_LEN (C66XX_DSP_5_L1P_SRAM_EADDR - C66XX_DSP_5_L1P_SRAM_SADDR + 1) 599 600 // CorePac5 L1D SRAM - 32KB 601 #define C66XX_DSP_5_L1D_SRAM_SADDR 0x15f00000 602 #define C66XX_DSP_5_L1D_SRAM_EADDR 0x15f07fff 603 #define C66XX_DSP_5_L1D_SRAM_LEN (C66XX_DSP_5_L1D_SRAM_EADDR - C66XX_DSP_5_L1D_SRAM_SADDR + 1) 604 605 // CorePac6 L2 SRAM (address to access from external masters) - 512KB 606 #define C66XX_DSP_6_L2_SRAM_SADDR 0x16800000 607 #define C66XX_DSP_6_L2_SRAM_EADDR 0x1687ffff 608 #define C66XX_DSP_6_L2_SRAM_LEN (C66XX_DSP_6_L2_SRAM_EADDR - C66XX_DSP_6_L2_SRAM_SADDR + 1) 609 610 // CorePac6 L1P SRAM - 32KB 611 #define C66XX_DSP_6_L1P_SRAM_SADDR 0x16e00000 612 #define C66XX_DSP_6_L1P_SRAM_EADDR 0x16e07fff 613 #define C66XX_DSP_6_L1P_SRAM_LEN (C66XX_DSP_6_L1P_SRAM_EADDR - C66XX_DSP_6_L1P_SRAM_SADDR + 1) 614 615 // CorePac6 L1D SRAM - 32KB 616 #define C66XX_DSP_6_L1D_SRAM_SADDR 0x16f00000 617 #define C66XX_DSP_6_L1D_SRAM_EADDR 0x16f07fff 618 #define C66XX_DSP_6_L1D_SRAM_LEN (C66XX_DSP_6_L1D_SRAM_EADDR - C66XX_DSP_6_L1D_SRAM_SADDR + 1) 619 620 // CorePac7 L2 SRAM (address to access from external masters) - 512KB 621 #define C66XX_DSP_7_L2_SRAM_SADDR 0x17800000 622 #define C66XX_DSP_7_L2_SRAM_EADDR 0x1787ffff 623 #define C66XX_DSP_7_L2_SRAM_LEN (C66XX_DSP_7_L2_SRAM_EADDR - C66XX_DSP_7_L2_SRAM_SADDR + 1) 624 625 // CorePac7 L1P SRAM - 32KB 626 #define C66XX_DSP_7_L1P_SRAM_SADDR 0x17e00000 627 #define C66XX_DSP_7_L1P_SRAM_EADDR 0x17e07fff 628 #define C66XX_DSP_7_L1P_SRAM_LEN (C66XX_DSP_7_L1P_SRAM_EADDR - C66XX_DSP_7_L1P_SRAM_SADDR + 1) 629 630 // CorePac7 L1D SRAM - 32KB 631 #define C66XX_DSP_7_L1D_SRAM_SADDR 0x17f00000 632 #define C66XX_DSP_7_L1D_SRAM_EADDR 0x17f07fff 633 #define C66XX_DSP_7_L1D_SRAM_LEN (C66XX_DSP_7_L1D_SRAM_EADDR - C66XX_DSP_7_L1D_SRAM_SADDR + 1) 634 635 // System trace manager (STM) configuration registers area - 1MB 636 #define C66XX_STM_RG_AREA_SADDR 0x20000000 637 #define C66XX_STM_RG_AREA_EADDR 0x200fffff 638 #define C66XX_STM_RG_AREA_LEN (C66XX_STM_RG_AREA_EADDR - C66XX_STM_RG_AREA_SADDR + 1) 639 640 // Boot ROM - 128KB 641 #define C66XX_BOOT_ROM_SADDR 0x20b00000 642 #define C66XX_BOOT_ROM_EADDR 0x20b1ffff 643 #define C66XX_BOOT_ROM_LEN (C66XX_BOOT_ROM_EADDR - C66XX_BOOT_ROM_SADDR + 1) 644 645 // SPI configuration registers area - 512B 646 #define C66XX_SPI_RG_AREA_SADDR 0x20bf0000 647 #define C66XX_SPI_RG_AREA_EADDR 0x20bf01ff 648 #define C66XX_SPI_RG_AREA_LEN (C66XX_SPI_RG_AREA_EADDR - C66XX_SPI_RG_AREA_SADDR + 1) 649 650 // EMIF16 configuration registers area - 256B 651 #define C66XX_EMIF16_RG_AREA_SADDR 0x20c00000 652 #define C66XX_EMIF16_RG_AREA_EADDR 0x20c000ff 653 #define C66XX_EMIF16_RG_AREA_LEN (C66XX_EMIF16_RG_AREA_EADDR - C66XX_EMIF16_RG_AREA_SADDR + 1) 654 655 // DDR3 EMIF configuration registers area - 512B 656 #define C66XX_DDR3_EMIF_RG_AREA_SADDR 0x21000000 657 #define C66XX_DDR3_EMIF_RG_AREA_EADDR 0x210001ff 658 #define C66XX_DDR3_EMIF_RG_AREA_LEN (C66XX_DDR3_EMIF_RG_AREA_EADDR - C66XX_DDR3_EMIF_RG_AREA_SADDR + 1) 659 660 // HyperLink configuration registers area - 256B 661 #define C66XX_HYPERLINK_RG_AREA_SADDR 0x21400000 662 #define C66XX_HYPERLINK_RG_AREA_EADDR 0x214000ff 663 #define C66XX_HYPERLINK_RG_AREA_LEN (C66XX_HYPERLINK_RG_AREA_EADDR - C66XX_HYPERLINK_RG_AREA_SADDR + 1) 664 665 // PCIe configuration registers area - 32KB 666 #define C66XX_PCIE_RG_AREA_SADDR 0x21800000 667 #define C66XX_PCIE_RG_AREA_EADDR 0x21807fff 668 #define C66XX_PCIE_RG_AREA_LEN (C66XX_PCIE_RG_AREA_EADDR - C66XX_PCIE_RG_AREA_SADDR + 1) 669 670 // Queue manager subsystem (QMSS) data area - 2MB 671 #define C66XX_QMSS_DATA_AREA_SADDR 0x34000000 672 #define C66XX_QMSS_DATA_AREA_EADDR 0x341fffff 673 #define C66XX_QMSS_DATA_AREA_LEN (C66XX_QMSS_DATA_AREA_EADDR - C66XX_QMSS_DATA_AREA_SADDR + 1) 674 675 // HyperLink data area - 256MB 676 #define C66XX_HYPERLINK_DATA_AREA_SADDR 0x40000000 677 #define C66XX_HYPERLINK_DATA_AREA_EADDR 0x4fffffff 678 #define C66XX_HYPERLINK_DATA_AREA_LEN (C66XX_HYPERLINK_DATA_AREA_EADDR - C66XX_HYPERLINK_DATA_AREA_SADDR + 1) 679 680 // PCIe data area - 256MB 681 #define C66XX_PCIE_DATA_AREA_SADDR 0x60000000 682 #define C66XX_PCIE_DATA_AREA_EADDR 0x6fffffff 683 #define C66XX_PCIE_DATA_AREA_LEN (C66XX_PCIE_DATA_AREA_EADDR - C66XX_PCIE_DATA_AREA_SADDR + 1) 684 685 // EMIF16 CE0 area - 64MB 686 #define C66XX_EMIF16_CE0_AREA_SADDR 0x70000000 687 #define C66XX_EMIF16_CE0_AREA_EADDR 0x73ffffff 688 #define C66XX_EMIF16_CE0_AREA_LEN (C66XX_EMIF16_CE0_AREA_EADDR - C66XX_EMIF16_CE0_AREA_SADDR + 1) 689 690 // EMIF16 CE1 area - 64MB 691 #define C66XX_EMIF16_CE1_AREA_SADDR 0x74000000 692 #define C66XX_EMIF16_CE1_AREA_EADDR 0x77ffffff 693 #define C66XX_EMIF16_CE1_AREA_LEN (C66XX_EMIF16_CE1_AREA_EADDR - C66XX_EMIF16_CE1_AREA_SADDR + 1) 694 695 // EMIF16 CE2 area - 64MB 696 #define C66XX_EMIF16_CE2_AREA_SADDR 0x78000000 697 #define C66XX_EMIF16_CE2_AREA_EADDR 0x7bffffff 698 #define C66XX_EMIF16_CE2_AREA_LEN (C66XX_EMIF16_CE2_AREA_EADDR - C66XX_EMIF16_CE2_AREA_SADDR + 1) 699 700 // EMIF16 CE3 area - 64MB 701 #define C66XX_EMIF16_CE3_AREA_SADDR 0x7c000000 702 #define C66XX_EMIF16_CE3_AREA_EADDR 0x7fffffff 703 #define C66XX_EMIF16_CE3_AREA_LEN (C66XX_EMIF16_CE3_AREA_EADDR - C66XX_EMIF16_CE3_AREA_SADDR + 1) 704 705 // DDR3 EMIF data area - 2GB 706 #define C66XX_DDR3_AREA_SADDR 0x80000000 707 #define C66XX_DDR3_AREA_EADDR 0xffffffff 708 #define C66XX_DDR3_AREA_LEN (C66XX_DDR3_AREA_EADDR - C66XX_DDR3_AREA_SADDR + 1) 709 710 //============================================================================= 711 #endif /* __C66XX_SELECT_C6678_DSP__ */ 712 713 714 715 //============================================================================= 716 //============ DSP core registers ============================================= 717 //============================================================================= 718 // DSP CorePack revision register - r-only 719 #define C66XX_CORE_MM_REVID_RG_ADDR 0x01812000 720 721 //------------ DSP CorePack revision register defs ---------------------------- 722 #define C66XX_CORE_MM_REVID_VERSION_BITMASK 0xffff0000 723 #define C66XX_CORE_MM_REVID_VERSION_BITSHIFT 16 724 #define C66XX_CORE_MM_REVID_REVISION_BITMASK 0x0000ffff 725 #define C66XX_CORE_MM_REVID_REVISION_BITSHIFT 0 726 727 #define C66XX_CORE_MM_REVID_VERSION_C6678 0x0008 728 #define C66XX_CORE_MM_REVID_REVISION_1_0 0x0 729 #define C66XX_CORE_MM_REVID_REVISION_2_0 0x1 730 731 732 // DSP interrupt controller registers addresses 733 734 // DSP Event Flag register 0 - r-only 735 #define C66XX_CORE_EVTFLAG0_RG_ADDR 0x01800000 736 // DSP Event Flag register 1 - r-only 737 #define C66XX_CORE_EVTFLAG1_RG_ADDR 0x01800004 738 // DSP Event Flag register 2 - r-only 739 #define C66XX_CORE_EVTFLAG2_RG_ADDR 0x01800008 740 // DSP Event Flag register 3 - r-only 741 #define C66XX_CORE_EVTFLAG3_RG_ADDR 0x0180000c 742 // DSP Event Set register 0 - r/w 743 #define C66XX_CORE_EVTSET0_RG_ADDR 0x01800020 744 // DSP Event Set register 1 - r/w 745 #define C66XX_CORE_EVTSET1_RG_ADDR 0x01800024 746 // DSP Event Set register 2 - r/w 747 #define C66XX_CORE_EVTSET2_RG_ADDR 0x01800028 748 // DSP Event Set register 3 - r/w 749 #define C66XX_CORE_EVTSET3_RG_ADDR 0x0180002c 750 // DSP Event Clear register 0 - r/w 751 #define C66XX_CORE_EVTCLR0_RG_ADDR 0x01800040 752 // DSP Event Clear register 1 - r/w 753 #define C66XX_CORE_EVTCLR1_RG_ADDR 0x01800044 754 // DSP Event Clear register 2 - r/w 755 #define C66XX_CORE_EVTCLR2_RG_ADDR 0x01800048 756 // DSP Event Clear register 3 - r/w 757 #define C66XX_CORE_EVTCLR3_RG_ADDR 0x0180004c 758 // DSP Event Mask register 0 - r/w 759 #define C66XX_CORE_EVTMASK0_RG_ADDR 0x01800080 760 // DSP Event Mask register 1 - r/w 761 #define C66XX_CORE_EVTMASK1_RG_ADDR 0x01800084 762 // DSP Event Mask register 2 - r/w 763 #define C66XX_CORE_EVTMASK2_RG_ADDR 0x01800088 764 // DSP Event Mask register 3 - r/w 765 #define C66XX_CORE_EVTMASK3_RG_ADDR 0x0180008c 766 767 // DSP Event Flag registers base address 768 #define C66XX_CORE_EVTFLAG_RG_BADDR 0x01800000 769 // DSP Event Flag registers offset 770 #define C66XX_CORE_EVTFLAG_RG_OFFSET 0x00000004 771 772 // DSP Event Set registers base address 773 #define C66XX_CORE_EVTSET_RG_BADDR 0x01800020 774 // DSP Event Set registers offset 775 #define C66XX_CORE_EVTSET_RG_OFFSET 0x00000004 776 777 // DSP Event Clear registers base address 778 #define C66XX_CORE_EVTCLR_RG_BADDR 0x01800040 779 // DSP Event Clear registers offset 780 #define C66XX_CORE_EVTCLR_RG_OFFSET 0x00000004 781 782 // DSP Event Mask registers base address 783 #define C66XX_CORE_EVTMASK_RG_BADDR 0x01800080 784 // DSP Event Mask registers offset 785 #define C66XX_CORE_EVTMASK_RG_OFFSET 0x00000004 786 787 //============================================================================= 788 789 790 791 //============================================================================= 792 //============ PLL controller registers ======================================= 793 //============================================================================= 794 // PLL control register - r/w 795 #define C66XX_PLL_PLLCTL_RG_OFFSET 0x100 796 // PLL secondary control register - r/w 797 #define C66XX_PLL_SECCTL_RG_OFFSET 0x108 798 // PLL multiplier control register - r/w 799 #define C66XX_PLL_PLLM_RG_OFFSET 0x110 800 // PLL controller divider 1 register - r/w 801 #define C66XX_PLL_PLLDIV1_RG_OFFSET 0x118 802 // PLL controller divider 2 register - r/w 803 #define C66XX_PLL_PLLDIV2_RG_OFFSET 0x11c 804 // PLL controller divider 3 register - r/w 805 #define C66XX_PLL_PLLDIV3_RG_OFFSET 0x120 806 // PLL controller command register - r/w 807 #define C66XX_PLL_PLLCMD_RG_OFFSET 0x138 808 // PLL controller status register - r/w 809 #define C66XX_PLL_PLLSTAT_RG_OFFSET 0x13c 810 // PLL controller clock align control register - r/w 811 #define C66XX_PLL_ALNCTL_RG_OFFSET 0x140 812 // PLL controller divider ratio change status register - r/w 813 #define C66XX_PLL_DCHANGE_RG_OFFSET 0x144 814 // SYSCLK status register - r-only 815 #define C66XX_PLL_SYSTAT_RG_OFFSET 0x150 816 // PLL controller divider 4 register - r/w 817 #define C66XX_PLL_PLLDIV4_RG_OFFSET 0x160 818 // PLL controller divider 5 register - r/w 819 #define C66XX_PLL_PLLDIV5_RG_OFFSET 0x164 820 // PLL controller divider 6 register - r/w 821 #define C66XX_PLL_PLLDIV6_RG_OFFSET 0x168 822 // PLL controller divider 7 register - r/w 823 #define C66XX_PLL_PLLDIV7_RG_OFFSET 0x16c 824 // PLL controller divider 8 register - r/w 825 #define C66XX_PLL_PLLDIV8_RG_OFFSET 0x170 826 // PLL controller divider 9 register - r/w 827 #define C66XX_PLL_PLLDIV9_RG_OFFSET 0x174 828 // PLL controller divider 10 register - r/w 829 #define C66XX_PLL_PLLDIV10_RG_OFFSET 0x178 830 // PLL controller divider 11 register - r/w 831 #define C66XX_PLL_PLLDIV11_RG_OFFSET 0x17c 832 // PLL controller divider 12 register - r/w 833 #define C66XX_PLL_PLLDIV12_RG_OFFSET 0x180 834 // PLL controller divider 13 register - r/w 835 #define C66XX_PLL_PLLDIV13_RG_OFFSET 0x184 836 // PLL controller divider 14 register - r/w 837 #define C66XX_PLL_PLLDIV14_RG_OFFSET 0x188 838 // PLL controller divider 15 register - r/w 839 #define C66XX_PLL_PLLDIV15_RG_OFFSET 0x18c 840 // PLL controller divider 16 register - r/w 841 #define C66XX_PLL_PLLDIV16_RG_OFFSET 0x190 842 843 #define C66XX_PLL_PLLCTL_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLCTL_RG_OFFSET) 844 #define C66XX_PLL_SECCTL_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_SECCTL_RG_OFFSET) 845 #define C66XX_PLL_PLLM_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLM_RG_OFFSET) 846 #define C66XX_PLL_PLLDIV1_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV1_RG_OFFSET) 847 #define C66XX_PLL_PLLDIV2_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV2_RG_OFFSET) 848 #define C66XX_PLL_PLLDIV3_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV3_RG_OFFSET) 849 #define C66XX_PLL_PLLCMD_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLCMD_RG_OFFSET) 850 #define C66XX_PLL_PLLSTAT_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLSTAT_RG_OFFSET) 851 #define C66XX_PLL_ALNCTL_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_ALNCTL_RG_OFFSET) 852 #define C66XX_PLL_DCHANGE_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_DCHANGE_RG_OFFSET) 853 #define C66XX_PLL_SYSTAT_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_SYSTAT_RG_OFFSET) 854 #define C66XX_PLL_PLLDIV4_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV4_RG_OFFSET) 855 #define C66XX_PLL_PLLDIV5_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV5_RG_OFFSET) 856 #define C66XX_PLL_PLLDIV6_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV6_RG_OFFSET) 857 #define C66XX_PLL_PLLDIV7_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV7_RG_OFFSET) 858 #define C66XX_PLL_PLLDIV8_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV8_RG_OFFSET) 859 #define C66XX_PLL_PLLDIV9_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV9_RG_OFFSET) 860 #define C66XX_PLL_PLLDIV10_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV10_RG_OFFSET) 861 #define C66XX_PLL_PLLDIV11_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV11_RG_OFFSET) 862 #define C66XX_PLL_PLLDIV12_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV12_RG_OFFSET) 863 #define C66XX_PLL_PLLDIV13_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV13_RG_OFFSET) 864 #define C66XX_PLL_PLLDIV14_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV14_RG_OFFSET) 865 #define C66XX_PLL_PLLDIV15_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV15_RG_OFFSET) 866 #define C66XX_PLL_PLLDIV16_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV16_RG_OFFSET) 867 868 869 //------------ PLL control register defs -------------------------------------- 870 #define C66XX_PLL_PLLCTL_PLLENSRC_BITMASK 0x20 871 #define C66XX_PLL_PLLCTL_PLLENSRC_BITSHIFT 5 872 #define C66XX_PLL_PLLCTL_PLLRST_BITMASK 0x8 873 #define C66XX_PLL_PLLCTL_PLLRST_BITSHIFT 3 874 #define C66XX_PLL_PLLCTL_PLLPWRDN_BITMASK 0x2 875 #define C66XX_PLL_PLLCTL_PLLPWRDN_BITSHIFT 1 876 #define C66XX_PLL_PLLCTL_PLLEN_BITMASK 0x1 877 #define C66XX_PLL_PLLCTL_PLLEN_BITSHIFT 0 878 879 880 //------------ PLL secondary control register defs ---------------------------- 881 #define C66XX_PLL_SECCTL_BYPASS_BITMASK 0x00800000 882 #define C66XX_PLL_SECCTL_BYPASS_BITSHIFT 23 883 #define C66XX_PLL_SECCTL_OUTPUT_DIVIDE_BITMASK 0x00780000 884 #define C66XX_PLL_SECCTL_OUTPUT_DIVIDE_BITSHIFT 19 885 886 887 //------------ PLL multiplier control register defs --------------------------- 888 #define C66XX_PLL_PLLM_PLLM_BITMASK 0x3f 889 #define C66XX_PLL_PLLM_PLLM_BITSHIFT 0 890 891 892 //------------ PLL controller divider registers defs -------------------------- 893 #define C66XX_PLL_PLLDIV_DEN_BITMASK 0x8000 894 #define C66XX_PLL_PLLDIV_DEN_BITSHIFT 15 895 #define C66XX_PLL_PLLDIV_RATIO_BITMASK 0xff 896 #define C66XX_PLL_PLLDIV_RATIO_BITSHIFT 0 897 898 899 //------------ PLL controller command register defs --------------------------- 900 #define C66XX_PLL_PLLCMD_GOSET_BITMASK 0x1 901 #define C66XX_PLL_PLLCMD_GOSET_BITSHIFT 0 902 903 904 //------------ PLL controller status register defs ---------------------------- 905 #define C66XX_PLL_PLLSTAT_GOSTAT_BITMASK 0x1 906 #define C66XX_PLL_PLLSTAT_GOSTAT_BITSHIFT 0 907 908 909 //------------ PLL controller clock align control register defs --------------- 910 #define C66XX_PLL_ALNCTL_ALN_BITMASK 0xffff 911 #define C66XX_PLL_ALNCTL_ALN_BITSHIFT 0 912 913 914 //------------ PLL controller divider ratio change status register defs ------- 915 #define C66XX_PLL_DCHANGE_SYS_BITMASK 0xffff 916 #define C66XX_PLL_DCHANGE_SYS_BITSHIFT 0 917 918 919 //------------ SYSCLK status register defs ------------------------------------ 920 #define C66XX_PLL_SYSTAT_SYSON_BITMASK 0xffff 921 #define C66XX_PLL_SYSTAT_SYSON_BITSHIFT 0 922 923 //============================================================================= 924 925 926 927 //============================================================================= 928 //============ Device State Control registers ================================= 929 //============================================================================= 930 /* 931 * !!! Note that this section contains only those definitions 932 * that are missed in TI C6000 Chip Support Library (CSL) !!! 933 */ 934 935 // JTAG ID register - r-only 936 #define C66XX_BOOTCFG_JTAGID_RG_OFFSET 0x18 937 // Device status register - r/w 938 #define C66XX_BOOTCFG_DEVSTAT_RG_OFFSET 0x20 939 // Boot kicker 0 register - r/w 940 #define C66XX_BOOTCFG_KICK0_RG_OFFSET 0x38 941 // Boot kicker 1 register - r/w 942 #define C66XX_BOOTCFG_KICK1_RG_OFFSET 0x3c 943 // DSP0 boot address register - r/w 944 #define C66XX_BOOTCFG_DSP_BOOT_ADDR0_RG_OFFSET 0x40 945 // DSP1 boot address register - r/w 946 #define C66XX_BOOTCFG_DSP_BOOT_ADDR1_RG_OFFSET 0x44 947 // DSP2 boot address register - r/w 948 #define C66XX_BOOTCFG_DSP_BOOT_ADDR2_RG_OFFSET 0x48 949 // DSP3 boot address register - r/w 950 #define C66XX_BOOTCFG_DSP_BOOT_ADDR3_RG_OFFSET 0x4c 951 // DSP4 boot address register - r/w 952 #define C66XX_BOOTCFG_DSP_BOOT_ADDR4_RG_OFFSET 0x50 953 // DSP5 boot address register - r/w 954 #define C66XX_BOOTCFG_DSP_BOOT_ADDR5_RG_OFFSET 0x54 955 // DSP6 boot address register - r/w 956 #define C66XX_BOOTCFG_DSP_BOOT_ADDR6_RG_OFFSET 0x58 957 // DSP7 boot address register - r/w 958 #define C66XX_BOOTCFG_DSP_BOOT_ADDR7_RG_OFFSET 0x5c 959 // MAC 1 address register - r-only 960 #define C66XX_BOOTCFG_MACID1_RG_OFFSET 0x110 961 // MAC 2 address register - r-only 962 #define C66XX_BOOTCFG_MACID2_RG_OFFSET 0x114 963 // LRESETNMI PIN status clear register - r/w 964 #define C66XX_BOOTCFG_LRSTNMIPINSTAT_CLR_RG_OFFSET 0x130 965 // Reset status clear register - r/w 966 #define C66XX_BOOTCFG_RESET_STAT_CLR_RG_OFFSET 0x134 967 // Boot complete register - r/w 968 #define C66XX_BOOTCFG_BOOTCOMPLETE_RG_OFFSET 0x13c 969 // Reset status register - r-only 970 #define C66XX_BOOTCFG_RESET_STAT_RG_OFFSET 0x144 971 // LRESETNMI PIN status register - r-only 972 #define C66XX_BOOTCFG_LRSTNMIPINSTAT_RG_OFFSET 0x148 973 // Device configuration register - r/w 974 #define C66XX_BOOTCFG_DEVCFG_RG_OFFSET 0x14c 975 // Power state control register - r/w 976 #define C66XX_BOOTCFG_PWRSTATECTL_RG_OFFSET 0x150 977 // SRIO SerDes macro status register - r-only 978 #define C66XX_BOOTCFG_SRIO_SERDES_STS_RG_OFFSET 0x154 979 // SMGII SerDes macro status register - r-only 980 #define C66XX_BOOTCFG_SMGII_SERDES_STS_RG_OFFSET 0x158 981 // PCIe SerDes macro status register - r-only 982 #define C66XX_BOOTCFG_PCIE_SERDES_STS_RG_OFFSET 0x15c 983 // HyperLink SerDes macro status register - r-only 984 #define C66XX_BOOTCFG_HYPERLINK_SERDES_STS_RG_OFFSET 0x160 985 // NMI generation for CorePac0 register - r/w 986 #define C66XX_BOOTCFG_NMIGR0_RG_OFFSET 0x200 987 // NMI generation for CorePac1 register - r/w 988 #define C66XX_BOOTCFG_NMIGR1_RG_OFFSET 0x204 989 // NMI generation for CorePac2 register - r/w 990 #define C66XX_BOOTCFG_NMIGR2_RG_OFFSET 0x208 991 // NMI generation for CorePac3 register - r/w 992 #define C66XX_BOOTCFG_NMIGR3_RG_OFFSET 0x20c 993 // NMI generation for CorePac4 register - r/w 994 #define C66XX_BOOTCFG_NMIGR4_RG_OFFSET 0x210 995 // NMI generation for CorePac5 register - r/w 996 #define C66XX_BOOTCFG_NMIGR5_RG_OFFSET 0x214 997 // NMI generation for CorePac6 register - r/w 998 #define C66XX_BOOTCFG_NMIGR6_RG_OFFSET 0x218 999 // NMI generation for CorePac7 register - r/w 1000 #define C66XX_BOOTCFG_NMIGR7_RG_OFFSET 0x21c 1001 // IPC generation for CorePac0 register - r/w 1002 #define C66XX_BOOTCFG_IPCGR0_RG_OFFSET 0x240 1003 // IPC generation for CorePac1 register - r/w 1004 #define C66XX_BOOTCFG_IPCGR1_RG_OFFSET 0x244 1005 // IPC generation for CorePac2 register - r/w 1006 #define C66XX_BOOTCFG_IPCGR2_RG_OFFSET 0x248 1007 // IPC generation for CorePac3 register - r/w 1008 #define C66XX_BOOTCFG_IPCGR3_RG_OFFSET 0x24c 1009 // IPC generation for CorePac4 register - r/w 1010 #define C66XX_BOOTCFG_IPCGR4_RG_OFFSET 0x250 1011 // IPC generation for CorePac5 register - r/w 1012 #define C66XX_BOOTCFG_IPCGR5_RG_OFFSET 0x254 1013 // IPC generation for CorePac6 register - r/w 1014 #define C66XX_BOOTCFG_IPCGR6_RG_OFFSET 0x258 1015 // IPC generation for CorePac7 register - r/w 1016 #define C66XX_BOOTCFG_IPCGR7_RG_OFFSET 0x25c 1017 1018 // Timer Input Selection register - r/w 1019 #define C66XX_BOOTCFG_TINPSEL_RG_OFFSET 0x300 1020 // Timer Output Selection register - r/w 1021 #define C66XX_BOOTCFG_TOUTPSEL_RG_OFFSET 0x304 1022 1023 // Main PLL Control register 0 - r/w 1024 #define C66XX_BOOTCFG_MAINPLLCTL0_RG_OFFSET 0x328 1025 // Main PLL Control register 1 - r/w 1026 #define C66XX_BOOTCFG_MAINPLLCTL1_RG_OFFSET 0x32c 1027 // DDR3 PLL Control register 0 - r/w 1028 #define C66XX_BOOTCFG_DDR3PLLCTL0_RG_OFFSET 0x330 1029 // DDR3 PLL Control register 1 - r/w 1030 #define C66XX_BOOTCFG_DDR3PLLCTL1_RG_OFFSET 0x334 1031 // Pass PLL Control register 0 - r/w 1032 #define C66XX_BOOTCFG_PASSPLLCTL0_RG_OFFSET 0x338 1033 // Pass PLL Control register 1 - r/w 1034 #define C66XX_BOOTCFG_PASSPLLCTL1_RG_OFFSET 0x33c 1035 // Device speed register - r-only 1036 #define C66XX_BOOTCFG_DEVSPEED_RG_OFFSET 0x3f8 1037 1038 #define C66XX_BOOTCFG_TINPSEL_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_TINPSEL_RG_OFFSET) 1039 #define C66XX_BOOTCFG_TOUTPSEL_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_TOUTPSEL_RG_OFFSET) 1040 #define C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_MAINPLLCTL0_RG_OFFSET) 1041 #define C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_MAINPLLCTL1_RG_OFFSET) 1042 #define C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_DDR3PLLCTL0_RG_OFFSET) 1043 #define C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_DDR3PLLCTL1_RG_OFFSET) 1044 #define C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_PASSPLLCTL0_RG_OFFSET) 1045 #define C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_PASSPLLCTL1_RG_OFFSET) 1046 #define C66XX_BOOTCFG_DEVSPEED_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_DEVSPEED_RG_OFFSET) 1047 1048 1049 //------------ Main PLL Control register 0 defs ------------------------------- 1050 #define C66XX_BOOTCFG_MAINPLLCTL0_BWADJ_BITMASK 0xff000000 1051 #define C66XX_BOOTCFG_MAINPLLCTL0_BWADJ_BITSHIFT 24 1052 #define C66XX_BOOTCFG_MAINPLLCTL0_PLLM_BITMASK 0x7f000 1053 #define C66XX_BOOTCFG_MAINPLLCTL0_PLLM_BITSHIFT 12 1054 #define C66XX_BOOTCFG_MAINPLLCTL0_PLLD_BITMASK 0x3f 1055 #define C66XX_BOOTCFG_MAINPLLCTL0_PLLD_BITSHIFT 0 1056 1057 1058 //------------ Main PLL Control register 1 defs ------------------------------- 1059 #define C66XX_BOOTCFG_MAINPLLCTL1_ENSAT_BITMASK 0x40 1060 #define C66XX_BOOTCFG_MAINPLLCTL1_ENSAT_BITSHIFT 6 1061 #define C66XX_BOOTCFG_MAINPLLCTL1_BWADJ_BITMASK 0xf 1062 #define C66XX_BOOTCFG_MAINPLLCTL1_BWADJ_BITSHIFT 0 1063 1064 1065 //------------ DDR3 PLL Control register 0 defs ------------------------------- 1066 #define C66XX_BOOTCFG_DDR3PLLCTL0_BWADJ_BITMASK 0xff000000 1067 #define C66XX_BOOTCFG_DDR3PLLCTL0_BWADJ_BITSHIFT 24 1068 #define C66XX_BOOTCFG_DDR3PLLCTL0_BYPASS_BITMASK 0x800000 1069 #define C66XX_BOOTCFG_DDR3PLLCTL0_BYPASS_BITSHIFT 23 1070 #define C66XX_BOOTCFG_DDR3PLLCTL0_PLLM_BITMASK 0x7ffc0 1071 #define C66XX_BOOTCFG_DDR3PLLCTL0_PLLM_BITSHIFT 6 1072 #define C66XX_BOOTCFG_DDR3PLLCTL0_PLLD_BITMASK 0x3f 1073 #define C66XX_BOOTCFG_DDR3PLLCTL0_PLLD_BITSHIFT 0 1074 1075 1076 //------------ DDR3 PLL Control register 1 defs ------------------------------- 1077 #define C66XX_BOOTCFG_DDR3PLLCTL1_PLLRST_BITMASK 0x2000 1078 #define C66XX_BOOTCFG_DDR3PLLCTL1_PLLRST_BITSHIFT 13 1079 #define C66XX_BOOTCFG_DDR3PLLCTL1_ENSAT_BITMASK 0x40 1080 #define C66XX_BOOTCFG_DDR3PLLCTL1_ENSAT_BITSHIFT 6 1081 #define C66XX_BOOTCFG_DDR3PLLCTL1_BWADJ_BITMASK 0xf 1082 #define C66XX_BOOTCFG_DDR3PLLCTL1_BWADJ_BITSHIFT 0 1083 1084 1085 //------------ PASS PLL Control register 0 defs ------------------------------- 1086 #define C66XX_BOOTCFG_PASSPLLCTL0_BWADJ_BITMASK 0xff000000 1087 #define C66XX_BOOTCFG_PASSPLLCTL0_BWADJ_BITSHIFT 24 1088 #define C66XX_BOOTCFG_PASSPLLCTL0_BYPASS_BITMASK 0x800000 1089 #define C66XX_BOOTCFG_PASSPLLCTL0_BYPASS_BITSHIFT 23 1090 #define C66XX_BOOTCFG_PASSPLLCTL0_PLLM_BITMASK 0x7ffc0 1091 #define C66XX_BOOTCFG_PASSPLLCTL0_PLLM_BITSHIFT 6 1092 #define C66XX_BOOTCFG_PASSPLLCTL0_PLLD_BITMASK 0x3f 1093 #define C66XX_BOOTCFG_PASSPLLCTL0_PLLD_BITSHIFT 0 1094 1095 1096 //------------ PASS PLL Control register 1 defs ------------------------------- 1097 #define C66XX_BOOTCFG_PASSPLLCTL1_PLLRST_BITMASK 0x4000 1098 #define C66XX_BOOTCFG_PASSPLLCTL1_PLLRST_BITSHIFT 14 1099 #define C66XX_BOOTCFG_PASSPLLCTL1_PLLSELECT_BITMASK 0x2000 1100 #define C66XX_BOOTCFG_PASSPLLCTL1_PLLSELECT_BITSHIFT 13 1101 #define C66XX_BOOTCFG_PASSPLLCTL1_ENSAT_BITMASK 0x40 1102 #define C66XX_BOOTCFG_PASSPLLCTL1_ENSAT_BITSHIFT 6 1103 #define C66XX_BOOTCFG_PASSPLLCTL1_BWADJ_BITMASK 0xf 1104 #define C66XX_BOOTCFG_PASSPLLCTL1_BWADJ_BITSHIFT 0 1105 1106 1107 //------------ Device speed register defs ------------------------------------- 1108 #define C66XX_BOOTCFG_DEVSPEED_DEVSPEED_BITMASK 0xff800000 1109 #define C66XX_BOOTCFG_DEVSPEED_DEVSPEED_BITSHIFT 23 1110 1111 // DSP core speed defs in MHz 1112 #define C66XX_DSP_CORE_SPEED_800MHZ 800 1113 #define C66XX_DSP_CORE_SPEED_1000MHZ 1000 1114 #define C66XX_DSP_CORE_SPEED_1200MHZ 1200 1115 #define C66XX_DSP_CORE_SPEED_1250MHZ 1250 1116 #define C66XX_DSP_CORE_SPEED_1400MHZ 1400 1117 1118 1119 //------------ MACID2 register defs ------------------------------------------- 1120 #define C66XX_BOOTCFG_MACID2_MACID_BITMASK 0xffff 1121 #define C66XX_BOOTCFG_MACID2_MACID_BITSHIFT 0 1122 1123 //============================================================================= 1124 1125 1126 1127 //============================================================================= 1128 //============ Power & sleep controller definitions =========================== 1129 //============================================================================= 1130 /* 1131 * !!! Note that this section contains only those definitions 1132 * that are missed in TI C6000 Chip Support Library (CSL) !!! 1133 */ 1134 1135 // Power Domains Definitions 1136 #define C66XX_PSC_PD_ALWAYSON 0 1137 #define C66XX_PSC_PD_TETB 1 1138 #define C66XX_PSC_PD_PA 2 1139 #define C66XX_PSC_PD_PCIE 3 1140 #define C66XX_PSC_PD_SRIO 4 1141 #define C66XX_PSC_PD_HYPERLINK 5 1142 #define C66XX_PSC_PD_MSM_SRAM 7 1143 #define C66XX_PSC_PD_DSP0 8 1144 #define C66XX_PSC_PD_DSP1 9 1145 #define C66XX_PSC_PD_DSP2 10 1146 #define C66XX_PSC_PD_DSP3 11 1147 #define C66XX_PSC_PD_DSP4 12 1148 #define C66XX_PSC_PD_DSP5 13 1149 #define C66XX_PSC_PD_DSP6 14 1150 #define C66XX_PSC_PD_DSP7 15 1151 #define C66XX_PSC_PD_COUNT (C66XX_PSC_PD_DSP7 + 1) 1152 1153 // Power Domains State Definitions 1154 #define C66XX_PSC_PD_STATE_OFF PSC_PDSTATE_OFF 1155 #define C66XX_PSC_PD_STATE_ON PSC_PDSTATE_ON 1156 1157 1158 // Power & Sleep Controller Clock Domains Definitions 1159 #define C66XX_PSC_LPSC_SHARED_LPSC 0 1160 #define C66XX_PSC_LPSC_SMARTREFLEX 1 1161 #define C66XX_PSC_LPSC_DDR3_EMIF 2 1162 #define C66XX_PSC_LPSC_EMIF16_SPI 3 1163 #define C66XX_PSC_LPSC_TSIP 4 1164 #define C66XX_PSC_LPSC_DEBUG_TRACE 5 1165 #define C66XX_PSC_LPSC_TETB 6 1166 #define C66XX_PSC_LPSC_PA 7 1167 #define C66XX_PSC_LPSC_ETHERNET 8 1168 #define C66XX_PSC_LPSC_SA 9 1169 #define C66XX_PSC_LPSC_PCIE 10 1170 #define C66XX_PSC_LPSC_SRIO 11 1171 #define C66XX_PSC_LPSC_HYPERLINK 12 1172 #define C66XX_PSC_LPSC_MSM_SRAM 14 1173 #define C66XX_PSC_LPSC_DSP0 15 1174 #define C66XX_PSC_LPSC_DSP1 16 1175 #define C66XX_PSC_LPSC_DSP2 17 1176 #define C66XX_PSC_LPSC_DSP3 18 1177 #define C66XX_PSC_LPSC_DSP4 19 1178 #define C66XX_PSC_LPSC_DSP5 20 1179 #define C66XX_PSC_LPSC_DSP6 21 1180 #define C66XX_PSC_LPSC_DSP7 22 1181 #define C66XX_PSC_LPSC_COUNT (C66XX_PSC_LPSC_DSP7 + 1) 1182 1183 // Clock Domains State Definitions 1184 #define C66XX_PSC_LPSC_STATE_OFF PSC_MODSTATE_SWRSTDISABLE 1185 #define C66XX_PSC_LPSC_STATE_ON PSC_MODSTATE_ENABLE 1186 1187 //============================================================================= 1188 1189 1190 1191 //============================================================================= 1192 //============ I2C definitions ================================================ 1193 //============================================================================= 1194 /* 1195 * !!! Note that this section contains only those definitions 1196 * that are missed in TI C6000 Chip Support Library (CSL) !!! 1197 */ 1198 1199 // I2C own address register - r/w 1200 #define C66XX_I2C_ICOAR_RG_OFFSET 0x00 1201 // I2C interrupt mask register - r/w 1202 #define C66XX_I2C_ICIMR_RG_OFFSET 0x04 1203 // I2C interrupt status register - r/w 1204 #define C66XX_I2C_ICSTR_RG_OFFSET 0x08 1205 // I2C clock low-time divider register - r/w 1206 #define C66XX_I2C_ICCLKL_RG_OFFSET 0x0c 1207 // I2C clock high-time divider register - r/w 1208 #define C66XX_I2C_ICCLKH_RG_OFFSET 0x10 1209 // I2C data count register - r/w 1210 #define C66XX_I2C_ICCNT_RG_OFFSET 0x14 1211 // I2C data receive register - r-only 1212 #define C66XX_I2C_ICDRR_RG_OFFSET 0x18 1213 // I2C slave address register - r/w 1214 #define C66XX_I2C_ICSAR_RG_OFFSET 0x1c 1215 // I2C data transmit register - r/w 1216 #define C66XX_I2C_ICDXR_RG_OFFSET 0x20 1217 // I2C mode register - r/w 1218 #define C66XX_I2C_ICMDR_RG_OFFSET 0x24 1219 // I2C interrupt vector register - r/w 1220 #define C66XX_I2C_ICIVR_RG_OFFSET 0x28 1221 // I2C extended mode register - r/w 1222 #define C66XX_I2C_ICEMDR_RG_OFFSET 0x2c 1223 // I2C prescaler register - r/w 1224 #define C66XX_I2C_ICPSC_RG_OFFSET 0x30 1225 // I2C peripheral identification 1 register - r/w 1226 #define C66XX_I2C_ICPID1_RG_OFFSET 0x34 1227 // I2C peripheral identification 2 register - r/w 1228 #define C66XX_I2C_ICPID2_RG_OFFSET 0x38 1229 1230 #define C66XX_I2C_ICOAR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICOAR_RG_OFFSET) 1231 #define C66XX_I2C_ICIMR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICIMR_RG_OFFSET) 1232 #define C66XX_I2C_ICSTR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICSTR_RG_OFFSET) 1233 #define C66XX_I2C_ICCLKL_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICCLKL_RG_OFFSET) 1234 #define C66XX_I2C_ICCLKH_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICCLKH_RG_OFFSET) 1235 #define C66XX_I2C_ICCNT_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICCNT_RG_OFFSET) 1236 #define C66XX_I2C_ICDRR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICDRR_RG_OFFSET) 1237 #define C66XX_I2C_ICSAR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICSAR_RG_OFFSET) 1238 #define C66XX_I2C_ICDXR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICDXR_RG_OFFSET) 1239 #define C66XX_I2C_ICMDR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICMDR_RG_OFFSET) 1240 #define C66XX_I2C_ICIVR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICIVR_RG_OFFSET) 1241 #define C66XX_I2C_ICEMDR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICEMDR_RG_OFFSET) 1242 #define C66XX_I2C_ICPSC_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICPSC_RG_OFFSET) 1243 #define C66XX_I2C_ICPID1_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICPID1_RG_OFFSET) 1244 #define C66XX_I2C_ICPID2_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICPID2_RG_OFFSET) 1245 1246 1247 //------------ I2C own address register defs ---------------------------------- 1248 #define C66XX_I2C_ICOAR_OADDR_BITMASK 0x3ff 1249 #define C66XX_I2C_ICOAR_OADDR_BITSHIFT 0 1250 1251 1252 //------------ I2C interrupt mask register defs ------------------------------- 1253 #define C66XX_I2C_ICIMR_AAS_BITMASK 0x40 1254 #define C66XX_I2C_ICIMR_AAS_BITSHIFT 6 1255 #define C66XX_I2C_ICIMR_SCD_BITMASK 0x20 1256 #define C66XX_I2C_ICIMR_SCD_BITSHIFT 5 1257 #define C66XX_I2C_ICIMR_ICXRDY_BITMASK 0x10 1258 #define C66XX_I2C_ICIMR_ICXRDY_BITSHIFT 4 1259 #define C66XX_I2C_ICIMR_ICRDRDY_BITMASK 0x8 1260 #define C66XX_I2C_ICIMR_ICRDRDY_BITSHIFT 3 1261 #define C66XX_I2C_ICIMR_ARDY_BITMASK 0x4 1262 #define C66XX_I2C_ICIMR_ARDY_BITSHIFT 2 1263 #define C66XX_I2C_ICIMR_NACK_BITMASK 0x2 1264 #define C66XX_I2C_ICIMR_NACK_BITSHIFT 1 1265 #define C66XX_I2C_ICIMR_AL_BITMASK 0x1 1266 #define C66XX_I2C_ICIMR_AL_BITSHIFT 0 1267 #define C66XX_I2C_ICIMR_RG_BITMASK 0x7f 1268 1269 1270 //------------ I2C interrupt status register defs ----------------------------- 1271 #define C66XX_I2C_ICSTR_SDIR_BITMASK 0x4000 1272 #define C66XX_I2C_ICSTR_SDIR_BITSHIFT 14 1273 #define C66XX_I2C_ICSTR_NACKSNT_BITMASK 0x2000 1274 #define C66XX_I2C_ICSTR_NACKSNT_BITSHIFT 13 1275 #define C66XX_I2C_ICSTR_BB_BITMASK 0x1000 1276 #define C66XX_I2C_ICSTR_BB_BITSHIFT 12 1277 #define C66XX_I2C_ICSTR_RSFULL_BITMASK 0x800 1278 #define C66XX_I2C_ICSTR_RSFULL_BITSHIFT 11 1279 #define C66XX_I2C_ICSTR_XSMT_BITMASK 0x400 1280 #define C66XX_I2C_ICSTR_XSMT_BITSHIFT 10 1281 #define C66XX_I2C_ICSTR_AAS_BITMASK 0x200 1282 #define C66XX_I2C_ICSTR_AAS_BITSHIFT 9 1283 #define C66XX_I2C_ICSTR_AD0_BITMASK 0x100 1284 #define C66XX_I2C_ICSTR_AD0_BITSHIFT 8 1285 #define C66XX_I2C_ICSTR_SCD_BITMASK 0x20 1286 #define C66XX_I2C_ICSTR_SCD_BITSHIFT 5 1287 #define C66XX_I2C_ICSTR_ICXRDY_BITMASK 0x10 1288 #define C66XX_I2C_ICSTR_ICXRDY_BITSHIFT 4 1289 #define C66XX_I2C_ICSTR_ICRDRDY_BITMASK 0x8 1290 #define C66XX_I2C_ICSTR_ICRDRDY_BITSHIFT 3 1291 #define C66XX_I2C_ICSTR_ARDY_BITMASK 0x4 1292 #define C66XX_I2C_ICSTR_ARDY_BITSHIFT 2 1293 #define C66XX_I2C_ICSTR_NACK_BITMASK 0x2 1294 #define C66XX_I2C_ICSTR_NACK_BITSHIFT 1 1295 #define C66XX_I2C_ICSTR_AL_BITMASK 0x1 1296 #define C66XX_I2C_ICSTR_AL_BITSHIFT 0 1297 1298 1299 //------------ I2C clock low-time divider register defs ----------------------- 1300 #define C66XX_I2C_ICCLKL_ICCL_BITMASK 0xffff 1301 #define C66XX_I2C_ICCLKL_ICCL_BITSHIFT 0 1302 1303 1304 //------------ I2C clock high-time divider register defs ---------------------- 1305 #define C66XX_I2C_ICCLKH_ICCH_BITMASK 0xffff 1306 #define C66XX_I2C_ICCLKH_ICCH_BITSHIFT 0 1307 1308 1309 //------------ I2C data count register defs ----------------------------------- 1310 #define C66XX_I2C_ICCNT_ICDC_BITMASK 0xffff 1311 #define C66XX_I2C_ICCNT_ICDC_BITSHIFT 0 1312 1313 1314 //------------ I2C data receive register defs --------------------------------- 1315 #define C66XX_I2C_ICDRR_D_BITMASK 0xff 1316 #define C66XX_I2C_ICDRR_D_BITSHIFT 0 1317 1318 1319 //------------ I2C slave address register defs -------------------------------- 1320 #define C66XX_I2C_ICSAR_SADDR_BITMASK 0x3ff 1321 #define C66XX_I2C_ICSAR_SADDR_BITSHIFT 0 1322 1323 1324 //------------ I2C data transmit register defs -------------------------------- 1325 #define C66XX_I2C_ICDXR_D_BITMASK 0xff 1326 #define C66XX_I2C_ICDXR_D_BITSHIFT 0 1327 1328 1329 //------------ I2C mode register defs ----------------------------------------- 1330 #define C66XX_I2C_ICMDR_NACKMOD_BITMASK 0x8000 1331 #define C66XX_I2C_ICMDR_NACKMOD_BITSHIFT 15 1332 #define C66XX_I2C_ICMDR_FREE_BITMASK 0x4000 1333 #define C66XX_I2C_ICMDR_FREE_BITSHIFT 14 1334 #define C66XX_I2C_ICMDR_STT_BITMASK 0x2000 1335 #define C66XX_I2C_ICMDR_STT_BITSHIFT 13 1336 #define C66XX_I2C_ICMDR_STP_BITMASK 0x800 1337 #define C66XX_I2C_ICMDR_STP_BITSHIFT 11 1338 #define C66XX_I2C_ICMDR_MST_BITMASK 0x400 1339 #define C66XX_I2C_ICMDR_MST_BITSHIFT 10 1340 #define C66XX_I2C_ICMDR_TRX_BITMASK 0x200 1341 #define C66XX_I2C_ICMDR_TRX_BITSHIFT 9 1342 #define C66XX_I2C_ICMDR_XA_BITMASK 0x100 1343 #define C66XX_I2C_ICMDR_XA_BITSHIFT 8 1344 #define C66XX_I2C_ICMDR_RM_BITMASK 0x80 1345 #define C66XX_I2C_ICMDR_RM_BITSHIFT 7 1346 #define C66XX_I2C_ICMDR_DLB_BITMASK 0x40 1347 #define C66XX_I2C_ICMDR_DLB_BITSHIFT 6 1348 #define C66XX_I2C_ICMDR_IRS_BITMASK 0x20 1349 #define C66XX_I2C_ICMDR_IRS_BITSHIFT 5 1350 #define C66XX_I2C_ICMDR_STB_BITMASK 0x10 1351 #define C66XX_I2C_ICMDR_STB_BITSHIFT 4 1352 #define C66XX_I2C_ICMDR_FDF_BITMASK 0x8 1353 #define C66XX_I2C_ICMDR_FDF_BITSHIFT 3 1354 #define C66XX_I2C_ICMDR_BC_BITMASK 0x7 1355 #define C66XX_I2C_ICMDR_BC_BITSHIFT 0 1356 1357 1358 //------------ I2C interrupt vector register defs ----------------------------- 1359 #define C66XX_I2C_ICIVR_INTCODE_BITMASK 0x7 1360 #define C66XX_I2C_ICIVR_INTCODE_BITSHIFT 0 1361 1362 1363 //------------ I2C extended mode register defs -------------------------------- 1364 #define C66XX_I2C_ICEMDR_IGNACK_BITMASK 0x2 1365 #define C66XX_I2C_ICEMDR_IGNACK_BITSHIFT 1 1366 #define C66XX_I2C_ICEMDR_BCM_BITMASK 0x1 1367 #define C66XX_I2C_ICEMDR_BCM_BITSHIFT 0 1368 1369 1370 //------------ I2C prescaler register defs ------------------------------------ 1371 #define C66XX_I2C_ICPSC_IPSC_BITMASK 0xff 1372 #define C66XX_I2C_ICPSC_IPSC_BITSHIFT 0 1373 1374 1375 //------------ I2C peripheral identification 1 register defs ------------------ 1376 #define C66XX_I2C_ICPID1_CLASS_BITMASK 0xff00 1377 #define C66XX_I2C_ICPID1_CLASS_BITSHIFT 8 1378 #define C66XX_I2C_ICPID1_REVISION_BITMASK 0xff 1379 #define C66XX_I2C_ICPID1_REVISION_BITSHIFT 0 1380 1381 1382 //------------ I2C peripheral identification 2 register defs ------------------ 1383 #define C66XX_I2C_ICPID2_TYPE_BITMASK 0xffff 1384 #define C66XX_I2C_ICPID2_TYPE_BITSHIFT 0 1385 1386 //============================================================================= 1387 1388 1389 1390 //============================================================================= 1391 //============ EMIF16 configuration registers ================================= 1392 //============================================================================= 1393 // Revision code and status register - r-only 1394 #define C66XX_EMIF16_RCSR_RG_OFFSET 0x00 1395 // Async wait cycle config register - r/w 1396 #define C66XX_EMIF16_AWCCR_RG_OFFSET 0x04 1397 // Async 1 (CE0) config register - r/w 1398 #define C66XX_EMIF16_A1CR_RG_OFFSET 0x10 1399 // Async 2 (CE1) config register - r/w 1400 #define C66XX_EMIF16_A2CR_RG_OFFSET 0x14 1401 // Async 3 (CE2) config register - r/w 1402 #define C66XX_EMIF16_A3CR_RG_OFFSET 0x18 1403 // Async 4 (CE3) config register - r/w 1404 #define C66XX_EMIF16_A4CR_RG_OFFSET 0x1c 1405 // Interrupt raw register - r/w 1406 #define C66XX_EMIF16_IRR_RG_OFFSET 0x40 1407 // Interrupt masked register - r/w 1408 #define C66XX_EMIF16_IMR_RG_OFFSET 0x44 1409 // Interrupt mask set register - r/w 1410 #define C66XX_EMIF16_IMSR_RG_OFFSET 0x48 1411 // Interrupt mask clear register - r/w 1412 #define C66XX_EMIF16_IMCR_RG_OFFSET 0x4c 1413 // Page mode control register - r/w 1414 #define C66XX_EMIF16_PMCR_RG_OFFSET 0x68 1415 1416 #define C66XX_EMIF16_RCSR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_RCSR_RG_OFFSET) 1417 #define C66XX_EMIF16_AWCCR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_AWCCR_RG_OFFSET) 1418 #define C66XX_EMIF16_A1CR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_A1CR_RG_OFFSET) 1419 #define C66XX_EMIF16_A2CR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_A2CR_RG_OFFSET) 1420 #define C66XX_EMIF16_A3CR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_A3CR_RG_OFFSET) 1421 #define C66XX_EMIF16_A4CR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_A4CR_RG_OFFSET) 1422 #define C66XX_EMIF16_IRR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_IRR_RG_OFFSET) 1423 #define C66XX_EMIF16_IMR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_IMR_RG_OFFSET) 1424 #define C66XX_EMIF16_IMSR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_IMSR_RG_OFFSET) 1425 #define C66XX_EMIF16_IMCR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_IMCR_RG_OFFSET) 1426 #define C66XX_EMIF16_PMCR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_PMCR_RG_OFFSET) 1427 1428 1429 //------------ Revision code and status register defs ------------------------- 1430 #define C66XX_EMIF16_RCSR_BE_BITMASK 0x80000000 1431 #define C66XX_EMIF16_RCSR_BE_BITSHIFT 31 1432 #define C66XX_EMIF16_RCSR_MOD_ID_BITMASK 0x3fff0000 1433 #define C66XX_EMIF16_RCSR_MOD_ID_BITSHIFT 16 1434 #define C66XX_EMIF16_RCSR_MJ_REV_BITMASK 0xff00 1435 #define C66XX_EMIF16_RCSR_MJ_REV_BITSHIFT 8 1436 #define C66XX_EMIF16_RCSR_MIN_REV_BITMASK 0xff 1437 #define C66XX_EMIF16_RCSR_MIN_REV_BITSHIFT 0 1438 1439 #define C66XX_EMIF16_RCSR_MOD_ID_DEFAULT_VALUE 0x46 1440 #define C66XX_EMIF16_RCSR_MJ_REV_DEFAULT_VALUE 0x4 1441 #define C66XX_EMIF16_RCSR_MIN_REV_DEFAULT_VALUE 0x0 1442 1443 1444 //------------ Async wait cycle config register defs -------------------------- 1445 #define C66XX_EMIF16_AWCCR_WP1_BITMASK 0x20000000 1446 #define C66XX_EMIF16_AWCCR_WP1_BITSHIFT 29 1447 #define C66XX_EMIF16_AWCCR_WP0_BITMASK 0x10000000 1448 #define C66XX_EMIF16_AWCCR_WP0_BITSHIFT 28 1449 #define C66XX_EMIF16_AWCCR_CS5_WAIT_BITMASK 0xc00000 1450 #define C66XX_EMIF16_AWCCR_CS5_WAIT_BITSHIFT 22 1451 #define C66XX_EMIF16_AWCCR_CS4_WAIT_BITMASK 0x300000 1452 #define C66XX_EMIF16_AWCCR_CS4_WAIT_BITSHIFT 20 1453 #define C66XX_EMIF16_AWCCR_CS3_WAIT_BITMASK 0xc0000 1454 #define C66XX_EMIF16_AWCCR_CS3_WAIT_BITSHIFT 18 1455 #define C66XX_EMIF16_AWCCR_CS2_WAIT_BITMASK 0x30000 1456 #define C66XX_EMIF16_AWCCR_CS2_WAIT_BITSHIFT 16 1457 #define C66XX_EMIF16_AWCCR_MAX_EXT_WAIT_BITMASK 0xff 1458 #define C66XX_EMIF16_AWCCR_MAX_EXT_WAIT_BITSHIFT 0 1459 1460 1461 //------------ Async 1 config register defs ----------------------------------- 1462 #define C66XX_EMIF16_A1CR_SS_BITMASK 0x80000000 1463 #define C66XX_EMIF16_A1CR_SS_BITSHIFT 31 1464 #define C66XX_EMIF16_A1CR_EW_BITMASK 0x40000000 1465 #define C66XX_EMIF16_A1CR_EW_BITSHIFT 30 1466 #define C66XX_EMIF16_A1CR_W_SETUP_BITMASK 0x3c000000 1467 #define C66XX_EMIF16_A1CR_W_SETUP_BITSHIFT 26 1468 #define C66XX_EMIF16_A1CR_W_STROBE_BITMASK 0x3f00000 1469 #define C66XX_EMIF16_A1CR_W_STROBE_BITSHIFT 20 1470 #define C66XX_EMIF16_A1CR_W_HOLD_BITMASK 0xe0000 1471 #define C66XX_EMIF16_A1CR_W_HOLD_BITSHIFT 17 1472 #define C66XX_EMIF16_A1CR_R_SETUP_BITMASK 0x1e000 1473 #define C66XX_EMIF16_A1CR_R_SETUP_BITSHIFT 13 1474 #define C66XX_EMIF16_A1CR_R_STROBE_BITMASK 0x1f80 1475 #define C66XX_EMIF16_A1CR_R_STROBE_BITSHIFT 7 1476 #define C66XX_EMIF16_A1CR_R_HOLD_BITMASK 0x70 1477 #define C66XX_EMIF16_A1CR_R_HOLD_BITSHIFT 4 1478 #define C66XX_EMIF16_A1CR_TA_BITMASK 0xc 1479 #define C66XX_EMIF16_A1CR_TA_BITSHIFT 2 1480 #define C66XX_EMIF16_A1CR_ASIZE_BITMASK 0x3 1481 #define C66XX_EMIF16_A1CR_ASIZE_BITSHIFT 0 1482 1483 #define C66XX_EMIF16_A1CR_ASIZE_8BIT 0 1484 #define C66XX_EMIF16_A1CR_ASIZE_16BIT 1 1485 1486 1487 //------------ Interrupt raw register defs ------------------------------------ 1488 #define C66XX_EMIF16_IRR_WR_BITMASK 0x3c 1489 #define C66XX_EMIF16_IRR_WR_BITSHIFT 2 1490 #define C66XX_EMIF16_IRR_AT_BITMASK 0x1 1491 #define C66XX_EMIF16_IRR_AT_BITSHIFT 0 1492 1493 1494 //------------ Interrupt masked register defs --------------------------------- 1495 #define C66XX_EMIF16_IMR_WR_MASKED_BITMASK 0x3c 1496 #define C66XX_EMIF16_IMR_WR_MASKED_BITSHIFT 2 1497 #define C66XX_EMIF16_IMR_AT_MASKED_BITMASK 0x1 1498 #define C66XX_EMIF16_IMR_AT_MASKED_BITSHIFT 0 1499 1500 1501 //------------ Interrupt mask set register defs ------------------------------- 1502 #define C66XX_EMIF16_IMSR_WR_MASK_SET_BITMASK 0x3c 1503 #define C66XX_EMIF16_IMSR_WR_MASK_SET_BITSHIFT 2 1504 #define C66XX_EMIF16_IMSR_AT_MASK_SET_BITMASK 0x1 1505 #define C66XX_EMIF16_IMSR_AT_MASK_SET_BITSHIFT 0 1506 1507 1508 //------------ Interrupt mask clear register defs ----------------------------- 1509 #define C66XX_EMIF16_IMCR_WR_MASK_CLR_BITMASK 0x3c 1510 #define C66XX_EMIF16_IMCR_WR_MASK_CLR_BITSHIFT 2 1511 #define C66XX_EMIF16_IMCR_AT_MASK_CLR_BITMASK 0x1 1512 #define C66XX_EMIF16_IMCR_AT_MASK_CLR_BITSHIFT 0 1513 1514 //============================================================================= 1515 1516 1517 1518 //============================================================================= 1519 //============ Timer definitions ============================================== 1520 //============================================================================= 1521 1522 // Emulation Management and Clock Speed register - r-only 1523 #define C66XX_TIMER_EMUMGT_CLKSPD_RG_OFFSET 0x0004 1524 // Counter register low register - r/w 1525 #define C66XX_TIMER_CNTLO_RG_OFFSET 0x0010 1526 // Counter register high register - r/w 1527 #define C66XX_TIMER_CNTHI_RG_OFFSET 0x0014 1528 // Period register low register - r/w 1529 #define C66XX_TIMER_PRDLO_RG_OFFSET 0x0018 1530 // Period register high register - r/w 1531 #define C66XX_TIMER_PRDHI_RG_OFFSET 0x001c 1532 // Timer control register - r/w 1533 #define C66XX_TIMER_TCR_RG_OFFSET 0x0020 1534 // Timer global control register - r/w 1535 #define C66XX_TIMER_TGCR_RG_OFFSET 0x0024 1536 // Watchdog timer control register - r/w 1537 #define C66XX_TIMER_WDTCR_RG_OFFSET 0x0028 1538 // Timer Reload register low register - r/w 1539 #define C66XX_TIMER_RELLO_RG_OFFSET 0x0034 1540 // Timer Reload register high register - r/w 1541 #define C66XX_TIMER_RELHI_RG_OFFSET 0x0038 1542 // Timer Capture register low register - r/w 1543 #define C66XX_TIMER_CAPLO_RG_OFFSET 0x003c 1544 // Timer Capture register high register - r/w 1545 #define C66XX_TIMER_CAPHI_RG_OFFSET 0x0040 1546 // Timer interrupt control and status register - r/w 1547 #define C66XX_TIMER_INTCTLSTAT_RG_OFFSET 0x0044 1548 1549 // Timer 0-15 registers area offset addresses 1550 #define C66XX_TIMER_RG_AREA_OFFSET 0x00010000 1551 // Timer 0-15 registers addresses: timer = 0-15 1552 #define C66XX_TIMER_EMUMGT_CLKSPD_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_EMUMGT_CLKSPD_RG_OFFSET) 1553 #define C66XX_TIMER_CNTLO_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_CNTLO_RG_OFFSET) 1554 #define C66XX_TIMER_CNTHI_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_CNTHI_RG_OFFSET) 1555 #define C66XX_TIMER_PRDLO_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_PRDLO_RG_OFFSET) 1556 #define C66XX_TIMER_PRDHI_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_PRDHI_RG_OFFSET) 1557 #define C66XX_TIMER_TCR_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_TCR_RG_OFFSET) 1558 #define C66XX_TIMER_TGCR_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_TGCR_RG_OFFSET) 1559 #define C66XX_TIMER_WDTCR_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_WDTCR_RG_OFFSET) 1560 #define C66XX_TIMER_RELLO_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_RELLO_RG_OFFSET) 1561 #define C66XX_TIMER_RELHI_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_RELHI_RG_OFFSET) 1562 #define C66XX_TIMER_CAPLO_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_CAPLO_RG_OFFSET) 1563 #define C66XX_TIMER_CAPHI_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_CAPHI_RG_OFFSET) 1564 #define C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_INTCTLSTAT_RG_OFFSET) 1565 1566 1567 //------------ Emulation Management and Clock Speed register defs ------------- 1568 #define C66XX_TIMER_EMUMGT_CLKSPD_CLKDIV_BITMASK 0x000f0000 1569 #define C66XX_TIMER_EMUMGT_CLKSPD_CLKDIV_BITSHIFT 16 1570 1571 1572 //------------ Timer control register defs ------------------------------------ 1573 #define C66XX_TIMER_TCR_READRSTMODE_HI_BITMASK 0x04000000 1574 #define C66XX_TIMER_TCR_READRSTMODE_HI_BITSHIFT 26 1575 #define C66XX_TIMER_TCR_ENAMODE_HI_BITMASK 0x00c00000 1576 #define C66XX_TIMER_TCR_ENAMODE_HI_BITSHIFT 22 1577 #define C66XX_TIMER_TCR_PWID_HI_BITMASK 0x00300000 1578 #define C66XX_TIMER_TCR_PWID_HI_BITSHIFT 20 1579 #define C66XX_TIMER_TCR_CP_HI_BITMASK 0x00080000 1580 #define C66XX_TIMER_TCR_CP_HI_BITSHIFT 19 1581 #define C66XX_TIMER_TCR_INVOUTP_HI_BITMASK 0x00020000 1582 #define C66XX_TIMER_TCR_INVOUTP_HI_BITSHIFT 17 1583 #define C66XX_TIMER_TCR_TSTAT_HI_BITMASK 0x00010000 1584 #define C66XX_TIMER_TCR_TSTAT_HI_BITSHIFT 16 1585 #define C66XX_TIMER_TCR_CAPEVTMODE_LO_BITMASK 0x00003000 1586 #define C66XX_TIMER_TCR_CAPEVTMODE_LO_BITSHIFT 12 1587 #define C66XX_TIMER_TCR_CAPMODE_LO_BITMASK 0x00000800 1588 #define C66XX_TIMER_TCR_CAPMODE_LO_BITSHIFT 11 1589 #define C66XX_TIMER_TCR_READRSTMODE_LO_BITMASK 0x00000400 1590 #define C66XX_TIMER_TCR_READRSTMODE_LO_BITSHIFT 10 1591 #define C66XX_TIMER_TCR_TIEN_LO_BITMASK 0x00000200 1592 #define C66XX_TIMER_TCR_TIEN_LO_BITSHIFT 9 1593 #define C66XX_TIMER_TCR_CLKSRC_LO_BITMASK 0x00000100 1594 #define C66XX_TIMER_TCR_CLKSRC_LO_BITSHIFT 8 1595 #define C66XX_TIMER_TCR_ENAMODE_LO_BITMASK 0x000000c0 1596 #define C66XX_TIMER_TCR_ENAMODE_LO_BITSHIFT 6 1597 #define C66XX_TIMER_TCR_PWID_LO_BITMASK 0x00000030 1598 #define C66XX_TIMER_TCR_PWID_LO_BITSHIFT 4 1599 #define C66XX_TIMER_TCR_CP_LO_BITMASK 0x00000008 1600 #define C66XX_TIMER_TCR_CP_LO_BITSHIFT 3 1601 #define C66XX_TIMER_TCR_INVINP_LO_BITMASK 0x00000004 1602 #define C66XX_TIMER_TCR_INVINP_LO_BITSHIFT 2 1603 #define C66XX_TIMER_TCR_INVOUTP_LO_BITMASK 0x00000002 1604 #define C66XX_TIMER_TCR_INVOUTP_LO_BITSHIFT 1 1605 #define C66XX_TIMER_TCR_TSTAT_LO_BITMASK 0x00000001 1606 #define C66XX_TIMER_TCR_TSTAT_LO_BITSHIFT 0 1607 1608 #define C66XX_TIMER_TCR_ENAMODE_DISABLED 0 1609 #define C66XX_TIMER_TCR_ENAMODE_ONE_SHOT 1 1610 #define C66XX_TIMER_TCR_ENAMODE_CONT 2 1611 #define C66XX_TIMER_TCR_ENAMODE_CONT_RELOAD 3 1612 1613 #define C66XX_TIMER_TCR_PWID_1_CLK 0 1614 #define C66XX_TIMER_TCR_PWID_2_CLK 1 1615 #define C66XX_TIMER_TCR_PWID_3_CLK 2 1616 #define C66XX_TIMER_TCR_PWID_4_CLK 3 1617 1618 #define C66XX_TIMER_TCR_CAPEVTMODE_RISING_EDGE 0 1619 #define C66XX_TIMER_TCR_CAPEVTMODE_FALLING_EDGE 1 1620 #define C66XX_TIMER_TCR_CAPEVTMODE_ANY_EDGE 2 1621 1622 1623 //------------ Timer global control register defs ----------------------------- 1624 #define C66XX_TIMER_TGCR_TDDRHI_BITMASK 0x0000f000 1625 #define C66XX_TIMER_TGCR_TDDRHI_BITSHIFT 12 1626 #define C66XX_TIMER_TGCR_PSCHI_BITMASK 0x00000f00 1627 #define C66XX_TIMER_TGCR_PSCHI_BITSHIFT 8 1628 #define C66XX_TIMER_TGCR_PLUSEN_BITMASK 0x00000010 1629 #define C66XX_TIMER_TGCR_PLUSEN_BITSHIFT 4 1630 #define C66XX_TIMER_TGCR_TIMMODE_BITMASK 0x0000000c 1631 #define C66XX_TIMER_TGCR_TIMMODE_BITSHIFT 2 1632 #define C66XX_TIMER_TGCR_TIMHIRS_BITMASK 0x00000002 1633 #define C66XX_TIMER_TGCR_TIMHIRS_BITSHIFT 1 1634 #define C66XX_TIMER_TGCR_TIMLORS_BITMASK 0x00000001 1635 #define C66XX_TIMER_TGCR_TIMLORS_BITSHIFT 0 1636 1637 #define C66XX_TIMER_TGCR_TIMMODE_64BIT_GPT 0 1638 #define C66XX_TIMER_TGCR_TIMMODE_32BIT_UNCHAINED 1 1639 #define C66XX_TIMER_TGCR_TIMMODE_64BIT_WDT 2 1640 #define C66XX_TIMER_TGCR_TIMMODE_32BIT_CHAINED 3 1641 1642 1643 //------------ Watchdog Timer Control Register defs --------------------------- 1644 #define C66XX_TIMER_WDTCR_WDKEY_BITMASK 0xffff0000 1645 #define C66XX_TIMER_WDTCR_WDKEY_BITSHIFT 16 1646 #define C66XX_TIMER_WDTCR_WDFLAG_BITMASK 0x00008000 1647 #define C66XX_TIMER_WDTCR_WDFLAG_BITSHIFT 15 1648 #define C66XX_TIMER_WDTCR_WDEN_BITMASK 0x00004000 1649 #define C66XX_TIMER_WDTCR_WDEN_BITSHIFT 14 1650 1651 #define C66XX_TIMER_WDTCR_WDKEY_FIRST_KEY 0xa5c6 1652 #define C66XX_TIMER_WDTCR_WDKEY_SECOND_KEY 0xda7e 1653 1654 1655 //------------ Timer interrupt control and status register defs --------------- 1656 #define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_HI_BITMASK 0x00080000 1657 #define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_HI_BITSHIFT 19 1658 #define C66XX_TIMER_INTCTLSTAT_EVTINTEN_HI_BITMASK 0x00040000 1659 #define C66XX_TIMER_INTCTLSTAT_EVTINTEN_HI_BITSHIFT 18 1660 #define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_HI_BITMASK 0x00020000 1661 #define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_HI_BITSHIFT 17 1662 #define C66XX_TIMER_INTCTLSTAT_PRDINTEN_HI_BITMASK 0x00010000 1663 #define C66XX_TIMER_INTCTLSTAT_PRDINTEN_HI_BITSHIFT 16 1664 #define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_LO_BITMASK 0x00000008 1665 #define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_LO_BITSHIFT 3 1666 #define C66XX_TIMER_INTCTLSTAT_EVTINTEN_LO_BITMASK 0x00000004 1667 #define C66XX_TIMER_INTCTLSTAT_EVTINTEN_LO_BITSHIFT 2 1668 #define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_LO_BITMASK 0x00000002 1669 #define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_LO_BITSHIFT 1 1670 #define C66XX_TIMER_INTCTLSTAT_PRDINTEN_LO_BITMASK 0x00000001 1671 #define C66XX_TIMER_INTCTLSTAT_PRDINTEN_LO_BITSHIFT 0 1672 1673 //============================================================================= 1674 1675 1676 1677 //============================================================================= 1678 #endif /* __C66XX_DEF_HXX__ */ 1679
