| /ThreadX-v6.4.1/ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/SSE-300-MPS3/ |
| D | fvp_sse300_mps3_s.sct | 30 * a separate 32 bytes aligned region so that the SAU can programmed to just
35 * area used to align this section on 32 bytes boundary (for SAU conf).
41 * This dummy region ensures that the next one will be aligned on a 32 bytes
|
| /ThreadX-v6.4.1/ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/ |
| D | fvp_sse300_mps3_s.sct | 30 * a separate 32 bytes aligned region so that the SAU can programmed to just
35 * area used to align this section on 32 bytes boundary (for SAU conf).
41 * This dummy region ensures that the next one will be aligned on a 32 bytes
|
| /ThreadX-v6.4.1/ports/arc_em/metaware/example_build/sample_threadx/ |
| D | sample_threadx.cmd | 13 IVT_SIZE_BYTES = IVT_SIZE_ITEMS * 4;//in bytes
|
| /ThreadX-v6.4.1/ports/arc_hs/metaware/example_build/sample_threadx/ |
| D | sample_threadx.cmd | 13 IVT_SIZE_BYTES = IVT_SIZE_ITEMS * 4;//in bytes
|
| /ThreadX-v6.4.1/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/ |
| D | sample_threadx.cmd | 13 IVT_SIZE_BYTES = IVT_SIZE_ITEMS * 4;//in bytes
|
| /ThreadX-v6.4.1/ports/cortex_m3/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 23 VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0
|
| /ThreadX-v6.4.1/ports/cortex_m0/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 23 VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0
|
| /ThreadX-v6.4.1/ports_module/cortex_m7/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 21 VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0
|
| /ThreadX-v6.4.1/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/ |
| D | sample_threadx.scat | 21 VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0
|
| /ThreadX-v6.4.1/ports/cortex_m4/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 21 VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0
|
| /ThreadX-v6.4.1/ports/cortex_m7/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 21 VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0
|
| /ThreadX-v6.4.1/ports_module/cortex_m4/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 21 VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0
|
| /ThreadX-v6.4.1/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/ |
| D | sample_threadx.scat | 21 VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0
|
| /ThreadX-v6.4.1/ports_module/cortex_m0+/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 21 VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0
|
| /ThreadX-v6.4.1/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/ |
| D | sample_threadx.scat | 21 VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0
|
| /ThreadX-v6.4.1/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/ |
| D | sample_threadx.scat | 21 VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0
|
| /ThreadX-v6.4.1/ports_module/cortex_m3/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 21 VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0
|
| /ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/ |
| D | init_caches2.mip | 68 li v1, 32 // Line size is always 32 bytes.
104 li v1, 32 // Line size is always 32 bytes.
162 sllv v1, a2, v1 // Now have true L2$ line size in bytes
201 sllv v1, a2, v1 // Decode L3$ line size in bytes
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| /ThreadX-v6.4.1/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/ |
| D | v7.S | 60 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
115 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
174 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
228 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
|
| /ThreadX-v6.4.1/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/ |
| D | v7.s | 60 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
115 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
174 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
228 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
|
| /ThreadX-v6.4.1/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/ |
| D | v7.s | 87 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
142 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
201 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
255 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
|
| /ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/ |
| D | v7.s | 87 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
142 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
201 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
255 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
|
| /ThreadX-v6.4.1/ports_smp/cortex_a7_smp/gnu/example_build/ |
| D | v7.S | 99 ADD r2, r2, #4 @ add 4 for the line length offset (log2 16 bytes)
157 ADD r2, r2, #4 @ add 4 for the line length offset (log2 16 bytes)
219 ADD r2, r2, #4 @ add 4 for the line length offset (log2 16 bytes)
275 ADD r2, r2, #4 @ add 4 for the line length offset (log2 16 bytes)
|
| /ThreadX-v6.4.1/ports_smp/cortex_a9_smp/gnu/example_build/ |
| D | startup.S | 293 @; SUB r1, r1, r0, LSL #8 ; 256 bytes of IRQ stack per CPU (0,1,2,3) - see …
298 @; SUB r1, r1, r0, LSL #12 ; 0x1000 bytes of App stack per CPU - see scatter…
306 …SUB r1, r1, r0, LSL #10 @ 1024 bytes of IRQ stack per CPU (0,1,2,3) - see sc…
313 …SUB r1, r1, r0, LSL #12 @ 0x1000 bytes of App stack per CPU - see scatter.sc…
|
| /ThreadX-v6.4.1/ports_smp/cortex_a5_smp/gnu/example_build/ |
| D | startup.S | 293 @; SUB r1, r1, r0, LSL #8 ; 256 bytes of IRQ stack per CPU (0,1,2,3) - see …
298 @; SUB r1, r1, r0, LSL #12 ; 0x1000 bytes of App stack per CPU - see scatter…
306 …SUB r1, r1, r0, LSL #10 @ 1024 bytes of IRQ stack per CPU (0,1,2,3) - see sc…
313 …SUB r1, r1, r0, LSL #12 @ 0x1000 bytes of App stack per CPU - see scatter.sc…
|
