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/ThreadX-v6.4.1/common/inc/
Dtx_thread.h73 #define TX_MOD32_BIT_SET(a,b) (b) = (((ULONG) 1) << ((a)%((UINT)32))); argument
78 #define TX_MOD32_BIT_SET(a,b) (b) = (((ULONG) 1) << ((a))); argument
88 #define TX_DIV32_BIT_SET(a,b) (b) = (((ULONG) 1) << ((a)/((UINT) 32))); argument
97 #define TX_THREAD_STATE_CHANGE(a, b) argument
155 #define TX_LOWEST_SET_BIT_CALCULATE(m, b) \ argument
156 (b) = ((ULONG) 0); \
163 (b) = (b) + ((ULONG) 2); \
165 (b) = (b) + ((m) >> ((ULONG) 1)); \
170 (b) = (b) + ((ULONG) 4); \
174 (b) = (b) + ((ULONG) 2); \
[all …]
/ThreadX-v6.4.1/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/
Dtx_initialize_low_level.s117 b _tx_memory_error
125 b _tx_instruction_error
133 b _tx_ev_machine_check
141 b _tx_ev_tblmiss_inst
149 b _tx_ev_tblmiss_data
157 b _tx_ev_protection_viol
165 b _tx_ev_privilege_viol
173 b _tx_ev_software_int
181 b _tx_ev_trap
189 b _tx_ev_extension
[all …]
/ThreadX-v6.4.1/ports/arc_hs/metaware/example_build/sample_threadx/
Dtx_initialize_low_level.s169 b _tx_memory_error
177 b _tx_instruction_error
185 b _tx_ev_machine_check
193 b _tx_ev_tblmiss_inst
201 b _tx_ev_tblmiss_data
209 b _tx_ev_protection_viol
217 b _tx_ev_privilege_viol
225 b _tx_ev_software_int
233 b _tx_ev_trap
241 b _tx_ev_extension
[all …]
/ThreadX-v6.4.1/ports/arc_em/metaware/example_build/sample_threadx/
Dtx_initialize_low_level.s200 b _tx_memory_error
208 b _tx_instruction_error
216 b _tx_ev_machine_check
224 b _tx_ev_tblmiss_inst
232 b _tx_ev_tblmiss_data
240 b _tx_ev_protection_viol
248 b _tx_ev_privilege_viol
256 b _tx_ev_software_int
264 b _tx_ev_trap
272 b _tx_ev_extension
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/
Dtx_boot.a6449 b _boot
52 b .
55 b .
58 b .
61 b .
64 b __tx_irq_handler
67 b .
70 b .
73 b .
76 b .
[all …]
/ThreadX-v6.4.1/ports/cortex_a53/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a53/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a55/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a55/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a57/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a57/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a34/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a35/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a35/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a72/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a72/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a73/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a73/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a75/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a65ae/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a65/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a65/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a75/gnu/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports/cortex_a76/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others
/ThreadX-v6.4.1/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/
Dv8_aarch64.S85 b.lt next_level // no data or unified cache at this level
104 b.ge loop_set
106 b.ge loop_way
110 b.gt loop_level
160 b.eq DynamIQ
162 b.eq DynamIQ
164 b.eq DynamIQ
166 b.eq DynamIQ
167 b Others

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