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/ThreadX-v6.4.1/ports/c667x/ccs/example_build/sample_threadx_c6678evm/
Dtx_initialize_low_level.asm35 ADDRESS_MSK .set 0xFFFFFFF0 ; Ensure 16-byte alignment
/ThreadX-v6.4.1/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/
Dtx_initialize_low_level.asm35 ADDRESS_MSK .set 0xFFFFFFF0 ; Ensure 16-byte alignment
/ThreadX-v6.4.1/ports/cortex_r5/ac6/example_build/sample_threadx/
Dtx_initialize_low_level.S132 SUB r1, r1, #1 @ Backup 1 byte
133 BIC r1, r1, #7 @ Ensure 8-byte alignment
141 SUB r1, r1, #1 @ Backup 1 byte
142 BIC r1, r1, #7 @ Ensure 8-byte alignment
148 SUB r1, r1, #1 @ Backup 1 byte
149 BIC r1, r1, #7 @ Ensure 8-byte alignment
/ThreadX-v6.4.1/ports/cortex_r5/gnu/example_build/
Dtx_initialize_low_level.S135 SUB r1, r1, #1 @ Backup 1 byte
136 BIC r1, r1, #7 @ Ensure 8-byte alignment
144 SUB r1, r1, #1 @ Backup 1 byte
145 BIC r1, r1, #7 @ Ensure 8-byte alignment
151 SUB r1, r1, #1 @ Backup 1 byte
152 BIC r1, r1, #7 @ Ensure 8-byte alignment
/ThreadX-v6.4.1/ports/arm9/gnu/example_build/
Dtx_initialize_low_level.S135 SUB r1, r1, #1 @ Backup 1 byte
136 BIC r1, r1, #7 @ Ensure 8-byte alignment
144 SUB r1, r1, #1 @ Backup 1 byte
145 BIC r1, r1, #7 @ Ensure 8-byte alignment
151 SUB r1, r1, #1 @ Backup 1 byte
152 BIC r1, r1, #7 @ Ensure 8-byte alignment
/ThreadX-v6.4.1/ports/arm11/gnu/example_build/
Dtx_initialize_low_level.S135 SUB r1, r1, #1 @ Backup 1 byte
136 BIC r1, r1, #7 @ Ensure 8-byte alignment
144 SUB r1, r1, #1 @ Backup 1 byte
145 BIC r1, r1, #7 @ Ensure 8-byte alignment
151 SUB r1, r1, #1 @ Backup 1 byte
152 BIC r1, r1, #7 @ Ensure 8-byte alignment
/ThreadX-v6.4.1/ports/cortex_r4/gnu/example_build/
Dtx_initialize_low_level.S135 SUB r1, r1, #1 @ Backup 1 byte
136 BIC r1, r1, #7 @ Ensure 8-byte alignment
144 SUB r1, r1, #1 @ Backup 1 byte
145 BIC r1, r1, #7 @ Ensure 8-byte alignment
151 SUB r1, r1, #1 @ Backup 1 byte
152 BIC r1, r1, #7 @ Ensure 8-byte alignment
/ThreadX-v6.4.1/ports/cortex_a5/ac5/example_build/
Dtx_initialize_low_level.s155 BIC r1, r1, #7 ; Ensure 8-byte alignment
163 BIC r1, r1, #7 ; Ensure 8-byte alignment
171 BIC r1, r1, #7 ; Ensure 8-byte alignment
217 BIC r1, r1, #7 ; Ensure 8-byte alignment
221 BIC r1, r1, #7 ; Ensure 8-byte alignment
224 BIC r1, r1, #7 ; Ensure 8-byte alignment
/ThreadX-v6.4.1/ports/cortex_a8/ac5/example_build/
Dtx_initialize_low_level.s155 BIC r1, r1, #7 ; Ensure 8-byte alignment
163 BIC r1, r1, #7 ; Ensure 8-byte alignment
171 BIC r1, r1, #7 ; Ensure 8-byte alignment
217 BIC r1, r1, #7 ; Ensure 8-byte alignment
221 BIC r1, r1, #7 ; Ensure 8-byte alignment
224 BIC r1, r1, #7 ; Ensure 8-byte alignment
/ThreadX-v6.4.1/ports/cortex_r5/ac5/example_build/
Dtx_initialize_low_level.s155 BIC r1, r1, #7 ; Ensure 8-byte alignment
163 BIC r1, r1, #7 ; Ensure 8-byte alignment
171 BIC r1, r1, #7 ; Ensure 8-byte alignment
217 BIC r1, r1, #7 ; Ensure 8-byte alignment
221 BIC r1, r1, #7 ; Ensure 8-byte alignment
224 BIC r1, r1, #7 ; Ensure 8-byte alignment
/ThreadX-v6.4.1/ports/cortex_r4/ac5/example_build/
Dtx_initialize_low_level.s155 BIC r1, r1, #7 ; Ensure 8-byte alignment
163 BIC r1, r1, #7 ; Ensure 8-byte alignment
171 BIC r1, r1, #7 ; Ensure 8-byte alignment
217 BIC r1, r1, #7 ; Ensure 8-byte alignment
221 BIC r1, r1, #7 ; Ensure 8-byte alignment
224 BIC r1, r1, #7 ; Ensure 8-byte alignment
/ThreadX-v6.4.1/ports/cortex_a7/ac5/example_build/
Dtx_initialize_low_level.s175 BIC r1, r1, #7 ; Ensure 8-byte alignment
183 BIC r1, r1, #7 ; Ensure 8-byte alignment
191 BIC r1, r1, #7 ; Ensure 8-byte alignment
237 BIC r1, r1, #7 ; Ensure 8-byte alignment
241 BIC r1, r1, #7 ; Ensure 8-byte alignment
244 BIC r1, r1, #7 ; Ensure 8-byte alignment
/ThreadX-v6.4.1/ports/cortex_a9/ac5/example_build/
Dtx_initialize_low_level.s175 BIC r1, r1, #7 ; Ensure 8-byte alignment
183 BIC r1, r1, #7 ; Ensure 8-byte alignment
191 BIC r1, r1, #7 ; Ensure 8-byte alignment
237 BIC r1, r1, #7 ; Ensure 8-byte alignment
241 BIC r1, r1, #7 ; Ensure 8-byte alignment
244 BIC r1, r1, #7 ; Ensure 8-byte alignment
/ThreadX-v6.4.1/ports_module/cortex_r4/iar/module_manager/src/
Dtxm_module_manager_user_mode_entry.s74 ; Save LR (and r3 for 8 byte aligned stack) and call the kernel dispatch function.
Dtxm_module_manager_thread_stack_build.s102 BIC r2, r2, #7 ; Ensure 8-byte alignment
/ThreadX-v6.4.1/ports_module/cortex_a7/ac5/module_manager/src/
Dtxm_module_manager_user_mode_entry.s73 ; Save LR (and r3 for 8 byte aligned stack) and call the kernel dispatch function.
/ThreadX-v6.4.1/ports_module/cortex_a7/iar/module_manager/src/
Dtxm_module_manager_user_mode_entry.s85 ; Save LR (and r3 for 8 byte aligned stack) and call the kernel dispatch function.
/ThreadX-v6.4.1/ports/arm9/ac5/example_build/
Dtx_initialize_low_level.s178 BIC r1, r1, #7 ; Ensure 8-byte alignment
186 BIC r1, r1, #7 ; Ensure 8-byte alignment
194 BIC r1, r1, #7 ; Ensure 8-byte alignment
254 BIC r1, r1, #7 ; Ensure 8-byte alignment
258 BIC r1, r1, #7 ; Ensure 8-byte alignment
261 BIC r1, r1, #7 ; Ensure 8-byte alignment
/ThreadX-v6.4.1/ports/arm11/ac5/example_build/
Dtx_initialize_low_level.s178 BIC r1, r1, #7 ; Ensure 8-byte alignment
186 BIC r1, r1, #7 ; Ensure 8-byte alignment
194 BIC r1, r1, #7 ; Ensure 8-byte alignment
254 BIC r1, r1, #7 ; Ensure 8-byte alignment
258 BIC r1, r1, #7 ; Ensure 8-byte alignment
261 BIC r1, r1, #7 ; Ensure 8-byte alignment
/ThreadX-v6.4.1/ports/cortex_a5/ghs/example_build/
Dtx_initialize_low_level.arm115 SUB r1, r1, 1 # Backup one byte
116 BIC r1, r1, 7 # Insure 8-byte alignment
124 SUB r1, r1, 1 # Backup one byte
125 BIC r1, r1, 7 # Insure 8-byte alignment
134 SUB r1, r1, 1 # Backup one byte
135 BIC r1, r1, 7 # Insure 8-byte alignment
/ThreadX-v6.4.1/ports/cortex_a8/ghs/example_build/
Dtx_initialize_low_level.arm115 SUB r1, r1, 1 # Backup one byte
116 BIC r1, r1, 7 # Insure 8-byte alignment
124 SUB r1, r1, 1 # Backup one byte
125 BIC r1, r1, 7 # Insure 8-byte alignment
134 SUB r1, r1, 1 # Backup one byte
135 BIC r1, r1, 7 # Insure 8-byte alignment
/ThreadX-v6.4.1/ports/cortex_a7/ghs/example_build/
Dtx_initialize_low_level.arm115 SUB r1, r1, 1 # Backup one byte
116 BIC r1, r1, 7 # Insure 8-byte alignment
124 SUB r1, r1, 1 # Backup one byte
125 BIC r1, r1, 7 # Insure 8-byte alignment
134 SUB r1, r1, 1 # Backup one byte
135 BIC r1, r1, 7 # Insure 8-byte alignment
/ThreadX-v6.4.1/ports/cortex_a9/ghs/example_build/
Dtx_initialize_low_level.arm115 SUB r1, r1, 1 # Backup one byte
116 BIC r1, r1, 7 # Insure 8-byte alignment
124 SUB r1, r1, 1 # Backup one byte
125 BIC r1, r1, 7 # Insure 8-byte alignment
134 SUB r1, r1, 1 # Backup one byte
135 BIC r1, r1, 7 # Insure 8-byte alignment
/ThreadX-v6.4.1/ports/cortex_r5/ghs/example_build/
Dtx_initialize_low_level.arm115 SUB r1, r1, 1 # Backup one byte
116 BIC r1, r1, 7 # Insure 8-byte alignment
124 SUB r1, r1, 1 # Backup one byte
125 BIC r1, r1, 7 # Insure 8-byte alignment
134 SUB r1, r1, 1 # Backup one byte
135 BIC r1, r1, 7 # Insure 8-byte alignment
/ThreadX-v6.4.1/ports/cortex_r7/ghs/example_build/
Dtx_initialize_low_level.arm115 SUB r1, r1, 1 # Backup one byte
116 BIC r1, r1, 7 # Insure 8-byte alignment
124 SUB r1, r1, 1 # Backup one byte
125 BIC r1, r1, 7 # Insure 8-byte alignment
134 SUB r1, r1, 1 # Backup one byte
135 BIC r1, r1, 7 # Insure 8-byte alignment

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