1 2 /**************************************************************************/ 3 /* Copyright (c) Cadence Design Systems, Inc. */ 4 /* */ 5 /* Permission is hereby granted, free of charge, to any person obtaining */ 6 /* a copy of this software and associated documentation files (the */ 7 /* "Software"), to deal in the Software without restriction, including */ 8 /* without limitation the rights to use, copy, modify, merge, publish, */ 9 /* distribute, sublicense, and/or sell copies of the Software, and to */ 10 /* permit persons to whom the Software is furnished to do so, subject to */ 11 /* the following conditions: */ 12 /* */ 13 /* The above copyright notice and this permission notice shall be */ 14 /* included in all copies or substantial portions of the Software. */ 15 /* */ 16 /* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, */ 17 /* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF */ 18 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */ 19 /* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY */ 20 /* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, */ 21 /* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE */ 22 /* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 /**************************************************************************/ 24 25 /************************************************************************** 26 27 RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES 28 29 This header is the primary glue between generic Xtensa RTOS support 30 sources and a specific RTOS port for Xtensa. It contains definitions 31 and macros for use primarily by Xtensa assembly coded source files. 32 33 Macros in this header map callouts from generic Xtensa files to specific 34 RTOS functions. It may also be included in C source files. 35 36 Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa 37 architecture, using the Xtensa hardware abstraction layer (HAL) to deal 38 with configuration specifics. 39 40 Should be included by all Xtensa generic and RTOS port-specific sources. 41 42 ***************************************************************************/ 43 44 #ifndef XTENSA_RTOS_H 45 #define XTENSA_RTOS_H 46 47 #ifdef __ASSEMBLER__ 48 #include <xtensa/coreasm.h> 49 #else 50 #include <stdint.h> 51 #include <xtensa/config/core.h> 52 #endif 53 54 #include <xtensa/corebits.h> 55 #include <xtensa/config/system.h> 56 #include <xtensa/simcall.h> 57 58 /* 59 Include any RTOS specific definitions that are needed by this header. 60 */ 61 #ifdef TX_INCLUDE_USER_DEFINE_FILE 62 #include "tx_user.h" 63 #endif 64 65 /* 66 Name of RTOS (for messages). 67 */ 68 #define XT_RTOS_NAME ThreadX 69 70 /* 71 Check some Xtensa configuration requirements and report error if not met. 72 Error messages can be customize to the RTOS port. 73 */ 74 75 #if !XCHAL_HAVE_XEA2 && !XCHAL_HAVE_XEA3 76 #error "ThreadX/Xtensa requires Xtensa Exception Architecture v2 (XEA2) or higher." 77 #endif 78 79 80 /*************************************************************************** 81 82 RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS. 83 84 Define callout macros used in generic Xtensa code to interact with the RTOS. 85 The macros are simply the function names for use in calls from assembler code. 86 Some of these functions may call back to generic functions in xtensa_context.h . 87 88 ***************************************************************************/ 89 90 /* 91 Inform RTOS of entry into an interrupt handler that will affect it. 92 Allows RTOS to manage switch to any system stack and count nesting level. 93 Called after minimal context has been saved, with interrupts disabled. 94 RTOS port can call0 _xt_context_save to save the rest of the context. 95 May only be called from assembly code by the 'call0' instruction. 96 */ 97 // void XT_RTOS_INT_ENTER(void) 98 #define XT_RTOS_INT_ENTER _tx_thread_context_save 99 100 /* 101 Inform RTOS of completion of an interrupt handler, and give control to 102 RTOS to perform thread/task scheduling, switch back from any system stack 103 and restore the context, and return to the exit dispatcher saved in the 104 stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore 105 to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save, 106 leaving only a minimal part of the context to be restored by the exit 107 dispatcher. This function does not return to the place it was called from. 108 May only be called from assembly code by the 'call0' instruction. 109 */ 110 // void XT_RTOS_INT_EXIT(void) 111 #define XT_RTOS_INT_EXIT _tx_thread_context_restore 112 113 /* 114 Convenience macros to disable and enable interrupts. 115 */ 116 #if XCHAL_HAVE_XEA3 117 #define XT_INTS_DISABLE(reg) movi reg, PS_DI; xps reg, reg 118 #define XT_INTS_ENABLE(reg) wsr reg, PS; rsync 119 #else 120 #define XT_INTS_DISABLE(reg) rsil reg, XCHAL_EXCM_LEVEL 121 #define XT_INTS_ENABLE(reg) wsr reg, PS; rsync 122 #endif 123 124 /* 125 Inform RTOS of the occurrence of a tick timer interrupt. 126 If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined. 127 May be coded in or called from C or assembly, per ABI conventions. 128 */ 129 #ifndef TX_NO_TIMER 130 // void XT_RTOS_TIMER_INT(void) 131 #define XT_RTOS_TIMER_INT _tx_timer_interrupt 132 #endif 133 134 /* 135 Return in a15 the base address of the co-processor state save area for the 136 thread that triggered a co-processor exception, or 0 if no thread was running. 137 The state save area is structured as defined in xtensa_context.h and has size 138 XT_CP_SIZE. Co-processor instructions should only be used in thread code, never 139 in interrupt handlers or the RTOS kernel. May only be called from assembly code 140 and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. 141 The implementation may use only a2-4, a15 (all other regs must be preserved). 142 */ 143 // void* XT_RTOS_CP_STATE(void) 144 #define XT_RTOS_CP_STATE _tx_thread_coproc_state 145 146 147 /*************************************************************************** 148 149 HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL. 150 151 This Xtensa RTOS port provides hooks for dynamically installing exception 152 and interrupt handlers to facilitate automated testing where each test 153 case can install its own handler for user exceptions and each interrupt 154 priority (level). This consists of an array of function pointers indexed 155 by interrupt priority, with index 0 being the user exception handler hook. 156 Each entry in the array is initially 0, and may be replaced by a function 157 pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0. 158 159 The handler for low and medium priority obeys ABI conventions so may be coded 160 in C. For the exception handler, the cause is the contents of the EXCCAUSE 161 reg, and the result is -1 if handled, else the cause (still needs handling). 162 For interrupt handlers, the cause is a mask of pending enabled interrupts at 163 that level, and the result is the same mask with the bits for the handled 164 interrupts cleared (those not cleared still need handling). This allows a test 165 case to either pre-handle or override the default handling for the exception 166 or interrupt level (see xtensa_vectors.S). 167 168 High priority handlers (including NMI) must be coded in assembly, are always 169 called by 'call0' regardless of ABI, must preserve all registers except a0, 170 and must not use or modify the interrupted stack. The hook argument 'cause' 171 is not passed and the result is ignored, so as not to burden the caller with 172 saving and restoring a2 (it assumes only one interrupt per level - see the 173 discussion in high priority interrupts in xtensa_vectors.S). The handler 174 therefore should be coded to prototype 'void h(void)' even though it plugs 175 into an array of handlers of prototype 'uint32_t h(uint32_t)'. 176 177 To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'. 178 179 ***************************************************************************/ 180 181 #define XT_INTEXC_HOOK_NUM (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI) 182 183 #ifndef __ASSEMBLER__ 184 typedef uint32_t (*XT_INTEXC_HOOK)(uint32_t cause); 185 extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM]; 186 #endif 187 188 189 /*************************************************************************** 190 191 CONVENIENCE INCLUSIONS. 192 193 Ensures RTOS specific files need only include this one Xtensa-generic header. 194 These headers are included last so they can use the RTOS definitions above. 195 196 ***************************************************************************/ 197 198 #include "xtensa_context.h" 199 200 #ifdef XT_RTOS_TIMER_INT 201 #include "xtensa_timer.h" 202 #endif 203 204 205 #endif /* XTENSA_RTOS_H */ 206 207