1 /***************************************************************************
2  * Copyright (c) 2024 Microsoft Corporation
3  *
4  * This program and the accompanying materials are made available under the
5  * terms of the MIT License which is available at
6  * https://opensource.org/licenses/MIT.
7  *
8  * SPDX-License-Identifier: MIT
9  **************************************************************************/
10 
11 #ifndef TM_PORTING_LAYER_H
12 #define TM_PORTING_LAYER_H
13 
14 #include <stdio.h>
15 
16 
17 /* Define the TRAP instruction. This is used by the Interrupt Processing and Interrupt Preemption Processing tests.
18    The SVC instruction below is for Cortex-M architectures using IAR tools. This will likely need to be modified
19    for different processors and/or development tools.
20 
21    Note also that for the Interrupt Processing test there is the assumption that the SVC ISR looks like:
22 
23     PUBLIC  SVC_Handler
24 SVC_Handler:
25     PUSH    {lr}
26     BL      tm_interrupt_handler
27     POP     {lr}
28     BX      LR
29 
30     And that for the Interrupt Preemption Processing test the SVC ISR looks like:
31 
32     PUBLIC  SVC_Handler
33 SVC_Handler:
34     PUSH    {lr}
35     BL      tm_interrupt_preemption_handler
36     POP     {lr}
37     BX      LR
38 
39    Again, this is very processor/tool specific so changes are likely needed for non Cortex-M/IAR
40    environments.  */
41 
42 #define TM_CAUSE_INTERRUPT    asm("SVC #0");
43 
44 
45 
46 #endif
47 
48