1#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc
2
3/* Secure Code */
4#define S_ROM_ALIAS               (0x11000000) /* SRAM_BASE_S */
5#define TOTAL_S_ROM_SIZE          (0x00080000) /* 128 kB */
6
7/* Secure Data */
8#define S_RAM_ALIAS               (0x31000000) /* ISRAM0_BASE_S */
9#define TOTAL_S_RAM_SIZE          (0x00220000) /* 256 kB */
10
11/* Non-Secure Code */
12#define NS_ROM_ALIAS              (0x01000000 + 0x00020000) /* SRAM_BASE_NS */
13#define TOTAL_NS_ROM_SIZE         (0x00020000) /* 128 kB */
14
15/* Non-Secure Data */
16#define NS_RAM_ALIAS              (0x21000000 + 0x00040000) /* ISRAM0_BASE_NS */
17#define TOTAL_NS_RAM_SIZE         (0x00040000) /* 256 kB */
18
19/* Heap and Stack sizes for secure and nonsecure applications */
20#define HEAP_SIZE                 (0x00000500) /* 1 KiB */
21#define STACK_SIZE                (0x00004100) /* 1 KiB */
22
23
24/* Secure regions */
25#define S_CODE_START     ( S_ROM_ALIAS )
26#define S_CODE_SIZE      ( TOTAL_S_ROM_SIZE )
27#define S_CODE_LIMIT     ( S_CODE_START + S_CODE_SIZE )
28
29#define S_DATA_START     ( S_RAM_ALIAS )
30#define S_DATA_SIZE      ( TOTAL_S_RAM_SIZE )
31#define S_DATA_LIMIT     ( S_DATA_START + S_DATA_SIZE )
32
33/* Non-Secure regions */
34#define NS_CODE_START    ( NS_ROM_ALIAS )
35#define NS_CODE_SIZE     ( TOTAL_NS_ROM_SIZE )
36#define NS_CODE_LIMIT    ( NS_CODE_START + NS_CODE_SIZE )
37
38#define NS_DATA_START    ( NS_RAM_ALIAS )
39#define NS_DATA_SIZE     ( TOTAL_NS_RAM_SIZE )
40#define NS_DATA_LIMIT    ( NS_DATA_START + NS_DATA_SIZE )
41
42LR_CODE S_CODE_START {
43    ER_CODE S_CODE_START {
44        *.o (RESET +First)
45        .ANY (+RO)
46    }
47
48    /* This empty, zero long execution region is here to mark the limit address
49     * of the last execution region that is allocated in SRAM.
50     */
51    CODE_WATERMARK +0 EMPTY 0x0 {
52    }
53    /* Make sure that the sections allocated in the SRAM does not exceed the
54     * size of the SRAM available.
55     */
56    ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE)
57
58    ER_DATA S_DATA_START {
59        .ANY (+ZI +RW)
60    }
61
62    #if HEAP_SIZE > 0
63    ARM_LIB_HEAP +0 ALIGN 8 EMPTY  HEAP_SIZE  {   ; Reserve empty region for heap
64    }
65    #endif
66
67    ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 {   ; Reserve empty region for stack
68    }
69
70    STACKSEAL +0 EMPTY 0x8 {
71    }
72
73    /* This empty, zero long execution region is here to mark the limit address
74     * of the last execution region that is allocated in SRAM.
75     */
76    SRAM_WATERMARK +0 EMPTY 0x0 {
77    }
78    /* Make sure that the sections allocated in the SRAM does not exceed the
79     * size of the SRAM available.
80     */
81    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
82}
83