1/*
2 * interAptiv/set_gpr_boot_values.S
3 *
4 *  Created on: May 9, 2012
5 *  Author: MIPS TECHNOLOGIES, INC
6 *  Set GPR values for interAptiv Family of Cores
7*/
8/*
9Unpublished work (c) MIPS Technologies, Inc.  All rights reserved.  Unpublished rights reserved
10under the copyright laws of the United States of America and other countries.
11
12This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
13may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
14Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
15not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
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18
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34This code may only be disclosed to the United States government ("Government"), or to
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45Technologies or an authorized third party.
46*/
47
48#include <boot.h>
49#include <m32c0.h>
50#include <regdef.h>
51#include <cps.h>
52
53// defines not yet in m32c0.h
54#define C0_MVPCTL $0, 1
55#define C0_MVPCONF0 $0, 2
56#define C0_VPECTL $1, 1
57#define C0_VPECONF0 $1, 2
58#define C0_TCSTATUS $2, 1
59#define C0_TCRESTART $2, 3
60#define C0_TCHALT $2, 4
61#define C0_TCBIND $2, 2
62
63	.set	noreorder           // Don't allow the assembler to reorder instructions.
64	.set	noat                // Don't allow the assembler to use r1(at) for synthetic instr.
65/**************************************************************************************
66**************************************************************************************/
67LEAF(set_gpr_boot_values)
68
69    li      r1_all_ones, 0xffffffff             // Simplify code and improve clarity
70    mfc0    a0, C0_EBASE                			// Read CP0 EBase
71	ext	    r23_cpu_num, a0, 0, 4     			// Extract CPUNum
72    li      r24_malta_word, MALTA_DISP_ADDR     // Need for reporting failed assertions.
73    la      gp, _gp                // All vpe share globals.
74    li      sp, STACK_BASE_ADDR     // Each vpe gets it's own stack.
75    ins     sp, r23_cpu_num, STACK_SIZE_LOG2, 3
76
77check_mt_ase:
78	mfc0	a0, C0_CONFIG1	        			// C0_Config1
79	bgez	a0, no_mt_ase             			// bit 31 sign bit set?
80	mfc0	a0, C0_CONFIG2	        			// C0_Config2
81	bgez	a0, no_mt_ase             			// bit 31 sign bit set?
82	mfc0	a0, C0_CONFIG3	        			// C0_Config3
83	and	    a0, (1 << 2)              			// M_Config3MT
84	beqz	a0, no_mt_ase
85    li      r10_has_mt_ase, 0
86
87has_mt_ase:
88    li      r10_has_mt_ase, 1
89
90    // Every vpe will set up the following to simplify resource initialization.
91    mfc0    a0, C0_TCBIND						// Read CP0 TCBind
92	ext	    r9_vpe_num, a0,  0, 4				// Extract CurVPE
93	ext	    r18_tc_num, a0, 21, 8				// Extract CurTC
94	mfc0    a0, C0_MVPCONF0						// C0_MVPConf0
95    ext	    r21_more_tcs, a0, 0, 8   			// Extract PTC
96    b       check_cps
97	ext	    r20_more_vpes, a0, 10, 4			// Extract VPE
98
99no_mt_ase: // This processor does not implement the MIPS32 MT ASE. Set up defaults.
100	sdbbp                                       // Failed assertion: not mt.
101
102check_cps: // Determine if there is a coherency manager present. (Implementation Dependent.)
103
104    mfc0    r25_coreid, C0_PRID					// CP0 PRId.
105    ext     a0, r25_coreid, 8, 16				// Extract Manuf and Core.
106    li      a3, 0x01A1							// interAptiv Multi core
107    beq     a3, a0, is_cps
108    nop
109
110is_not_interAptiv: // This processor is not a InterAptive Core so exit!
111	sdbbp                                       // Failed assertion: not interAptiv.
112
113is_cps:
114	li      r11_is_cps, 1
115
116    // Verify that we can find the GCRs.
117	la	    a1, GCR_CONFIG_ADDR					// KSEG1(GCRBASE)
118	lw	    a0, GCR_BASE(a1)					// read GCR_BASE
119        ins         a1, $0, 29, 3 					// Convert KSEG1 to physical address.
120	ins	    a0, $0, 0, 15					// Isolate physical base address of GCR (Clear lower bits).
121	beq	    a1, a0, gcr_found
122    nop
123    sdbbp   // Can't find GCR. RTL config override of MIPS default?
124
125gcr_found:
126    // Every vpe will set up the following to simplify resource initialization.
127    li      r22_gcr_addr, GCR_CONFIG_ADDR
128    lw      r8_core_num, (CORE_LOCAL_CONTROL_BLOCK + GCR_CL_ID) (r22_gcr_addr) // Load GCR_CL_ID
129    lw      a0, GCR_CONFIG(r22_gcr_addr)      // Load GCR_CONFIG
130	ext	    r19_more_cores, a0, PCORES, PCORES_S // Extract PCORES
131
132done_init_gpr:
133    jr     ra
134    nop
135END(set_gpr_boot_values)
136