1/*
2 * init_gpr.S
3 *
4 *  Created on: Jan 12, 2011
5 *      Author: MIPS TECHNOLOGIES, INC
6 *  Start of boot code for 24K Family of Cores
7*/
8/*
9Unpublished work (c) MIPS Technologies, Inc.  All rights reserved.  Unpublished rights reserved
10under the copyright laws of the United States of America and other countries.
11
12This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
13may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
14Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
15not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
16prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
17copyright laws. Violations thereof may result in criminal penalties and fines.
18
19MIPS Technologies reserves the right to change this code to improve function, design or
20otherwise. MIPS Technologies does not assume any liability arising out of the application or use
21of this code, or of any error or omission in such code.  Any warranties, whether express, statutory,
22implied or otherwise, including but not limited to the implied warranties of merchantability or
23fitness for a particular purpose, are excluded.  Except as expressly provided in any written license
24agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
25not give recipient any license to any intellectual property rights, including any patent rights, that
26cover this code.
27
28This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
29violation of the law of any country or international law, regulation, treaty, Executive Order,
30statute, amendments or supplements thereto.  Should a conflict arise regarding the export,
31reexport, transfer, or release of this code, the laws of the United States of America shall be
32the governing law.
33
34This code may only be disclosed to the United States government ("Government"), or to
35Government users, with prior written consent from MIPS Technologies or an authorized third
36party.  This code constitutes one or more of the following: commercial computer software,
37commercial computer software documentation or other commercial items.  If the user of this
38code, or any related documentation of any kind, including related technical data or manuals, is an
39agency, department, or other entity of the Government, the use, duplication, reproduction, release,
40modification, disclosure, or transfer of this code, or any related documentation of any kind, is
41restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
42Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies.  The use of
43this code by the Government is further restricted in accordance with the terms of the license
44agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
45Technologies or an authorized third party.
46*/
47#include <boot.h>
48#include <regdef.h>
49#include <m32c0.h>
50
51	.set	noreorder           // Don't allow the assembler to reorder instructions.
52	.set	noat                // Don't allow the assembler to use r1(at) for synthetic instr.
53/**************************************************************************************
54**************************************************************************************/
55LEAF(init_gpr)
56
57	// Initialize the general purpose registers and any shadow register sets.
58	// Although not necessary, register initialization may be useful during boot,
59    // debug, and simulation when certain ways of initializing registers may not work
60    // (xor rN, rN, rN for example.)
61
62	// Initialize register sets
63    li      $1, 0xdeadbeef      // (0xdeadbeef stands out, kseg2 mapped, odd.)
64
65	// Determine how many shadow sets are implemented (in addition to the base register set.)
66	// the first time thru the loop it will initialize using $1 set above.
67	// At the bottom og the loop, 1 is  subtract from $30
68	// and loop back to next_shadow_set to start the next loop and the next lowest set number.
69	mfc0	$29, C0_SRSCTL		// read C0_SRSCtl
70	ext	    $30, $29, 26, 4		// extract HSS
71
72next_shadow_set:
73	// set PSS to shadow set to be initialized
74	ins	    $29, $30, 6, 4		// insert PSS
75	mtc0	$29, C0_SRSCTL		// write C0_SRSCtl
76
77	wrpgpr	$1, $1
78	wrpgpr	$2, $1
79	wrpgpr	$3, $1
80	wrpgpr	$4, $1
81	wrpgpr	$5, $1
82	wrpgpr	$6, $1
83	wrpgpr	$7, $1
84	wrpgpr	$8, $1
85	wrpgpr	$9, $1
86	wrpgpr	$10, $1
87	wrpgpr	$11, $1
88	wrpgpr	$12, $1
89	wrpgpr	$13, $1
90	wrpgpr	$14, $1
91	wrpgpr	$15, $1
92	wrpgpr	$16, $1
93	wrpgpr	$17, $1
94	wrpgpr	$18, $1
95	wrpgpr	$19, $1
96	wrpgpr	$20, $1
97	wrpgpr	$21, $1
98	wrpgpr	$22, $1
99	wrpgpr	$23, $1
100	wrpgpr	$24, $1
101	wrpgpr	$25, $1
102	wrpgpr	$26, $1
103	wrpgpr	$27, $1
104	wrpgpr	$28, $1
105	wrpgpr	$29, $1
106	beqz    $30, done_init_gpr // early exit when we get to set 0 so we don't clobber return in $31
107	nop
108	wrpgpr	$30, $1
109	wrpgpr	$31, $1
110	b	next_shadow_set
111	add	$30, -1  // Since the code started with the highest set number this decrements to the next lower number
112
113
114done_init_gpr:
115    jr      ra
116    nop
117END(init_gpr)
118
119